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PROGRAMMING INFORMATION
Table 2·10:
ICSR Commands (continued)
+- - - - - - - - -+- - - - - - - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - • - - - - - - - - • - - - -+
J
ICSR*
I COMMAND
I
DESCRIPTION
i
<07:00>
I
+- - - - - - - • ·+- - - - - - - - - - - - - - - - - - -+- - - - •• - - - - - •• - - - - - •• - - - - - - - - - - - -
-+
lOlOMMNN
lOllxxxx
llOOxxxx
lllOOLLL
CONTROL MODE BITS
M7:MS
PRESELECT IMR FOR
WRITING
PRESELECT ACR FOR
WRITING
PRESELECT RESPONSE
MEMORY FOR WRITING
Sets Mode Register bits
6
and
5
to the value
in
<06:05>.
Mode
Register
bit
7 is set according
to <01:00>, as follows:
01 00
Bit
7
..
-
-
..........
-
...
0
0
Unchanged
0
1
Set
1
0
Cleared
0
0
(illegal)
All future write operations to
the ICDR load the data
into
the
IMR.
All future write operations to
the ICDR load the data
into
the
ACR.
All future write operations to
the ICDR load the data
into
the
Response
Memory at the interrupt
request level location
specified
in <02:00>.
+· .. - .... ·+· - - . - - . - - . - - - - - - - .
-+- - - - - - • - - • - - - . - - - - - - - •... - ...•. -
·+
*
x
=
1
or 0 (doesn't matter)
2.1.5.3
IRR · The
8-bit
Interrupt
Request
Register
stores
pending
interrupt
requests.
An
IRR
bit
is
set
when
the
corresponding
interrrupt
request
line
is
asserted;
and
automatically
cleared when the request is acknowledged.
The IRR
bits can be read, set, and cleared through
the
ICSR
and
ICDR.
RESET clears the IRR.
2.1.5.4
IMR - The 8-bit
Interrupt
Mask
Register
is
used
to
enable
(bit
cleared)
or
disable
(bit
set) the corresponding
interrupt request lines.
~
set IMR bit does not disable the
IRR
bit,
and
the
request
will remain pending until the IMR bit is
cleared.
Only •Jnmasked interrupts generate the
Group
Interrupt
output.
All IMR bits are set by RESET.
2-10
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