Pci Express - Alpha Data ADM-PCIE-9V8 User Manual

3.3 PCI Express

The ADM-PCIE-9V8 is capable of PCIe Gen 3 with 8 lanes. The FPGA drives these lanes directly using the
Integrated PCI Express block from AMD. Negotiation of PCIe link speed and number of lanes used is generally
automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA through a buffer. See
PERST0_1V8_L.
The other pin assignments for the high speed lanes are provided in the pinout attached to the
Table
The PCI Express specification requires that all add-in cards be ready for enumeration within 120ms after power
is valid (100ms after power is valid + 20ms after PERST is released). The ADM-PCIE-9V8 does meet this
requirement when configured from a tandem bitstream with the proper SPI constraints detailed in the section:
Configuration From Flash Memory. For more details on tandem configuration, see AMD xapp 1179.
Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by AMD. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See AMD PG195, PG213, and PG239 for more details).
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ADM-PCIE-9V8 User Manual
Complete Pinout Table signal
Complete Pinout
Functional Description
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