Clocking; Figure 7 Clock Topology - Alpha Data ADM-PCIE-9V8 User Manual

3.2 Clocking

The ADM-PCIE-9V8 provides flexible reference clock solutions for the many multi-gigabit transceiver quads and
FPGA fabric. The reprogrammable clocks from the LMK61E2 are reconfigurable from the front panel
Interface by using Alpha Data's avr2util utility. This allows the user to configure almost any arbitrary clock
frequency during application run time. The maximum clock frequency for the LMK61e2 is 900MHz. There is also
an of embedding IP into the FPGA design that permits programmable clock re-configuration via PCIe or from
within the FPGA.
There are four Si5324 jitter attenuators. These can provide clean and synchronous clocks to all of the QSFP and
FireFly quad locations at many clock frequencies. The Si5324 can be reconfigured over I2C using a controller
embedded in the FPGA design.
All clock names in the section below can be found in
FPGA GPIO
SI5328_1V8_SDA
SI5328_1V8_SCL
SI5328_*_1V8_INT_C1B
SI5328_*_1V8_LOL
SI5328_*_RST_1V8_L
SI5328_0_IN1
(FPGA GPIO)
SI5328_1_IN1
(FPGA GPIO)
SI5328_2_IN1
(FPGA GPIO)
LMK61E2
Programmable
Source
50ppm
LMK61E2
Programmable
Source
50ppm
200MHz
Fixed
Source
25ppm
PCIe
Edge
U36
(ASFLMPLV-
100.000MHZ-LR-T)
Page 8
I2C +
Si5328_0
CLKOUT1
CNTRL
Crystal
(2.5V VCC)
XA/XB CLKOUT2
114.285MHz
Address: 1101000
CLKIN1
CMODE = GND
CLKIN2
I2C +
Si5328_1
CLKOUT1
CNTRL
Crystal
(2.5V VCC)
XA/XB CLKOUT2
114.285MHz
Address: 1101001
CLKIN1
CMODE = GND
CLKIN2
I2C +
Si5328_2
CLKOUT1
CNTRL
Crystal
(2.5V VCC)
XA/XB CLKOUT2
114.285MHz
Address: 1101010
CLKIN1
CMODE = GND
CLKIN2
Buffer
NB6L14SMNG
Buffer
NB6L14SMNG
PCIE_REFCLK, 100MHz std. MGTREFCLK0_224)
PCIE_LCL_REFCLK, 100MHz std. (MGTREFCLK0_225)
Figure 7 : Clock Topology
Complete Pinout Table.
QSFP-DD side of FPGA
SI5328_0_OUT1 (MGTREFCLK0)
NC (MGTREFCLK1)
QSFP-DD_CLK (MGTREFCLK0)
NC (MGTREFCLK1)
SI5328_0_OUT2 (MGTREFCLK0)
SI5328_0_CLKIN2 (MGTREFCLK1)
QSFP-DD_CLK (MGTREFCLK0)
NC (MGTREFCLK1)
SI5328_1_OUT1 (MGTREFCLK0)
SI5328_1_CLKIN2 (MGTREFCLK1)
QSFP-DD_CLK (MGTREFCLK0)
NC (MGTREFCLK1)
SI5328_1_OUT2 (MGTREFCLK0)
NC (MGTREFCLK1)
QSFP-DD_CLK (MGTREFCLK0)
NC (MGTREFCLK1)
FireFly side of FPGA
SI5328_2_OUT1 (MGTREFCLK0)
SI5328_2_CLKIN2 (MGTREFCLK1)
FIREFLY_CLK (MGTREFCLK0)
SI5328_2_IN (MGTREFCLK1)
SI5328_2_OUT2 (MGTREFCLK0)
NC (MGTREFCLK1)
FIREFLY_CLK (MGTREFCLK0)
NC (MGTREFCLK1)
REFCLK200 (FABRIC_CLK) 200MHz Default (IO Bank)
ADM-PCIE-9V8 User Manual
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Functional Description
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