Firefly; Figure 10 Firefly Locations - Alpha Data ADM-PCIE-9V8 User Manual

ADM-PCIE-9V8 User Manual

3.5 FireFly

Trace lengths for the FireFly links and the associated estimated propagation delay for each lane is listed in
appendix Propagation Delays. These delays were calculated using the estimated propagation delay of Megtron 6
PCB laminate, which is 5.85ps/mm.
There are four FireFly sites available on the circuit board. The sites are capable of hosting either active optical or
passive copper FireFly connectors. The communication interface can run at up to 25Gbps per channel in either
cable type. There are 16 channels on the FireFly site (total maximum bandwidth of 400Gbps). This site is ideally
suited for 16x 10G/25G, 4x 100G Ethernet, or any other protocol supported by the Xilinx GTF Transceivers.
Please see AMD User Guide UG1549 for more details on the capabilities of the transceivers.
All FireFly site have control signals connected to the ACAP. Their connectivity is detailed in the Complete Pinout
Table at the end of this document. The notation used in the pin assignments is FIREFLY* with locations clarified
in the diagram below.
Figure 10 : FireFly Locations
The management interface of each FireFly module is connected directly to the FPGA. Each low speed sideband
signals (MODPRS, INT_L, RST_L, SDA, SCL) has an external pull-up resistor.
Page 14 Functional Description
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