Qsfp-Dd; Figure 9 Qsfp-Dd Location - Alpha Data ADM-PCIE-9V8 User Manual

ADM-PCIE-9V8 User Manual

3.4 QSFP-DD

Trace lengths for the QSFP links and the associated estimated propagation delay for each lane is listed in
appendix Propagation
PCB laminate, which is 5.85ps/mm.
Four QSFP-DD cages are available at the front panel. These cages are capable of housing either QSFP28 or
QSFP-DD cables (backwards compatible). Both active optical and passive copper QSFP-DD/QSFP28
compatible models are fully compliant. The communication interface can run at up to 25Gbps per channel. Each
QSFP-DD cage has 8 channels (total maximum bandwidth of 200Gbps per cage). This cage is ideally suited for
8x 10G/25G, 2x 100G Ethernet, or any protocol supported by the AMD GTF Transceivers. Please see AMD User
Guide UG1549 for more details on the capabilities of the transceivers.
All QSFP-DD cages have control signals connected to the FPGA. Their connectivity is detailed in the
Pinout Table at the end of this document. The notation used in the pin assignments is QSFP_0*, QSFP_1*,
QSFP_2*, and QSFP_3*, with locations clarified in the diagram below.
The Management Interface of each QSFP-DD cage is connected to the FPGA, as detailed in
Table. The available signals are SDA/SCL (I2C), INT_L (interrupt), LPMODE (low power mode), RST_L (reset),
and MODPRS_L (module present).
Note:
The LPMODE (Low Power Mode) to the cage is pulled down by default.
Functional Description
ad-ug-1467_v1_0.pdf
Delays. These delays were calculated using the estimated propagation delay of Megtron 6
Figure 9 : QSFP-DD Location
Complete
Complete Pinout
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