Clocking; Pcie Reference Clocks; Fabric Clock; Figure 7 Clock Topology - Alpha Data ADM-PCIE-8K5-FH User Manual

ADM-PCIE-8K5-FH User Manual

3.2 Clocking

The ADM-PCIE-8K5-FH provides reference clocks for the DDR4 SDRAM banks and the I/O interfaces available
to the user. After a clock is programmed to a certain frequency, that frequency will become the default on
power-up. Any clock out of an Si5338 Clock Synthesizer is re-configurable over I2C. This allows the user to
configure almost any arbitrary clock frequencies during application run time. Please see the Alpha Data API
functions for examples of how this is done.
Note: use "set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]" to ensure the user
design does not interfere with the I2C interface to the reprogramable clock generator.
Card Edge PCIe
Ref Clock (100MHz)
25MHz
20ppm
Source
200MHz, 30ppm
Source
100MHz, 10ppm
Source
External Ref Clock

3.2.1 PCIe Reference Clocks

The 8 MGT lanes connected to the PCIe card edge use MGT tiles 224/225 and use the system 100 MHz clock
(PCIE_REFCLK).
A second PCIe reference clock is buffered up from the edge to the FireFly module MGT tiles (231/232).
PCIE_REFCLK_1
PCIE_REFCLK_2

3.2.2 Fabric Clock

The design offers a fabric clock called FABRIC_CLK which is permanently fixed at 200 MHz. This clock is
intended to be used for IDELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC)
pin.
Functional Description
ad-ug-1342_v1_0.pdf
NB6L11S
Fanout
Si5338
Clock NB6L11S
Synth
Fanout
Figure 7 : Clock Topology
Signal Target FPGA Input
MGTREFCLK1_231
MGTREFCLK0_224
Table 5 : PCIe Reference Clocks
PCIe Ref Clock_1 (MGTREFCLK0_224)
PCIe Ref Clock_2 (MGTREFCLK1_231)
SFP0 156.25MHz Factory Default (MGTREFCLK0_127)
SFP1 156.25MHz Factory Default (MGTREFCLK0_228)
Memory Interface Clock 300Mhz (IO Bank 66)
Memory Interface Clock 300Mhz (IO Bank 44)
FireFly 156.25MHz Factory Default (MGTREFCLK0_232)
FABRIC_CLK 200MHz (IO Bank 64)
EMCCLK 100MHz (IO Bank 65)
Ext Ref Clock (MGTREFCLK1_232)
I/O Standard "P" pin
LVDS H10
LVDS AT10
"N" pin
H9
AT9
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