Schematics, Layout And Bom; Schematic Diagram; Figure 6-1. Pmic Schematic - Texas Instruments LP87725Q1EVM User Manual

Schematics, Layout and BOM

6 Schematics, Layout and BOM
This section contains the schematics, layout and the bill of materials for the LP87725Q1EVM.

6.1 Schematic Diagram

This section includes images of the EVM schematics and different layers of the layout.
J4 PVIN_3V3
PVIN3V3PRE
1 2
VOUT3V3PRE
3 4
5 6
TP1
3V3PS 7 8
J5 3V3_USB C5
16V
VOUT3V3USB 0.22µF
3.3V, 6 A
J1
1
TP2
2
C1
C2 C3 C4
16V 25V
10V 10V
0.1uF 22uF 22uF
100uF
GND
NT1
Net-Tie
NT2
Net-Tie
NT3
Net-Tie
AGND GND
NT4
Net-Tie
J7
nERR_WD_DIS_DIG
R1
VBATPRE
nERR_WD_DIS
23.7k
R52
0
D5
8.2V
GND
PMIC Enable Header
J6 EN_LVPMIC
EN_LV_PMIC_USB PGOOD_PREREG
J3 EN_PVIN_3V3
R4
PVIN3V3 100k
EN_LV_PMIC
GND
I2C Header
J34 I2C_CONN VIO
R59
10k
SCL_I2C_MCU SCL_I2C_LS
SCL_I2C
VIO
R23
10k
SDA_I2C_MCU SDA_I2C_LS
SDA_I2C
12 LP87725Q1EVM Evaluation Module
R7 0
L2 PVIN3V3
4.7uH
1 2 C14
C13 C17
R9
L1 6.3V 16V
16V
0.47
C7 20m 22µF 0.22µF 0.1uF
6.3V
PMIC Circuit Schematic
C10
4.7uF
6.3V
22µF
U1
23
PVIN_B1
GND
21
C20
PVIN_B2
9
16V PVIN_B3
1uF
GND
17
VCCA
C6 C8 C9
C11 C12 C16
10V 10V 6.3V
10V 6.3V 6.3V 15
VOUT_VLDO
10uF 10uF 10uF 4.7uF 4.7uF
4.7uF C19
16V
1uF
7
ENABLE
PVIN3V3
GND
1
SCL
R11
0
3
SDA
5
RSTOUT
C18
C15
6.3V 6.3V
19
ERR/WD_DIS
2.2µF 2.2µF
12
PVIN_LDO_LS1
14
PVIN_LS2/INT/GPI
AGND
R16 1.00k LP87725101RAGRQ1
EN_LV_PMIC
R14 0
SCL_I2C PVIN3V3
R13 0
SDA_I2C
R22 0
nRSTOUT
nINT_GPO
R15 0 C88 C89
nERR_WD_DIS
6.3V 6.3V
2.2µF
2.2µF
PVIN3V3
3
2 GND
1
VOUT_1V2_Filter
C60 C87
6.3V 6.3V
J9
2.2µF 2.2µF
GND
SYNC Clock, VMON2 Header
VIO
R10
J10 SYNCCLK_VMON2
20.0k
1
J14 nINT_GPO
SYNCCLKIN_MCU
2
VMON2_SYNCCLK 3
R17 R41
VOUT_1V2_Filter nINT_GPO_MCU
8.25k 100k
GND
nINT_GPO
VIO Header J8 VIO_SEL
R58
VIO
4.7k
MCUVCC PVIN3V3
J12 NRST
VIO
VMON1 Header
nRSTOUT_MCU
R5 R8
VOUT_1V8_Filter nRSTOUT
100k 8.25k
J13 VMON1_SEL
GND
1
2
VIO
VOUT_LDO_LS1

Figure 6-1. PMIC Schematic

Copyright © 2023 Texas Instruments Incorporated
R24 0
FBB1
L4 VOUT_1V8
470nH
C22 C26 C32 C35
SWB1
24
16V 10V 10V 10V
SW_B1
FBB1
2 10uF 10µF 10µF
0.22µF
FB_B1
SWB2
20
SW_B2 R26 0
FBB2 FBB2 GND
18
L6
FB_B2
VOUT_1V0
SWB3
8
SW_B3 470nH
FBB3
6 C23
FB_B3 C27 C30 C34
16V 10V 10V 10V
10uF
0.22µF 10uF 10µF
11
VOUT_LDO_LS1/VMON1
R25 0
FBB3 GND
13
VOUT_LS2/VMON2/SYNCCLK L5
VOUT_1V2
4
AGND
470nH
16 C24 C28 C31
AGND C36
10 16V 10V 10V 10V
PGND_B3
0.22µF 10uF 10µF 10uF
22
PGND_B12
TP3
GND
1 GND AGND
2
3 C21
C29 C25
TP4
6.3V 6.3V 10V
2.2µF 4.7uF 10µF
J15
TP5
GND
C33
C37 C90
TP6
10V 6.3V 16V
0.1uF
10µF 2.2µF
GND
Watchdog Disable, Digital Interface Headers
nINT_GPO_LS
J16 nERR_WD_DIS
R21
100k
GND
nERR_WD_DIS_MCU nERR_WD_DIS_LS
nERR_WD_DIS_DIG
J2 WD_DIS
R3 1.2k
3
2
R2 4.7k
1
VIO
nRSTOUT_LS
GND
R19
100k
R18
20.0k
GND
C63
1
6.3V
10µF
VOUT_1V8
R30
TP7 49.9
FBB1 R6 0
C66
VOUT_1V8_Filter
NT8
L8 10m NT5 6.3V
Net-Tie
1 2
10µF
C42 C45 C48 C50 C53 C56 Net-Tie
6.3V 6.3V 6.3V 10V 16V 16V 2
R27 0
10µF 10µF 10µF 1µF 0.22uF C91
0.1uF 1
16V
C38
1uF
BUCK1
10V TP10
10µF
J28
C64
1
6.3V
L7 10m
10µF
GND
1 2
VOUT_1V0
R32
TP8
49.9
R28 0
FBB2 R12 0
C39
NT10
10V C67
VOUT_1V0_Filter
10uF Net-Tie
NT7 10µF
J26
C43 C46 C49 C52 C55 Net-Tie
6.3V 6.3V 6.3V 10V 16V 1
L9 10m
2
10µF 10µF 10µF 1µF 0.22uF C58
C61
1 2
16V TP11
16V
0.1uF BUCK2
1uF
R29 0
C40 J27
10V
C62
10uF 1
6.3V
GND
10µF
VOUT_1V2
VOUT_LDO_LS1 R31
TP9
49.9
FBB3 R20 0
C65 NT9
Net-Tie
J17 VOUT_1V2_Filter 6.3V
2 NT6 10µF
1
C47 C51
C41 C44 C54 Net-Tie J25
6.3V 6.3V 6.3V 10V 16V
1
VOUT_LDO_LS1
10µF 10µF 10µF 1µF 0.22uF
2
C57 C59 TP12
16V 16V
VMON2_SYNCCLK BUCK3
0.1uF 1uF
J18
GND
1
2
VOUT_LS2
FB Pin Headers
High dI/dt Power Connectors
J19
2 1
VOUT_1V8_Filter VOUT_1V8_Filter J21 FB_B1_S
4 3
1
6 5
VOUT_1V0_Filter VOUT_1V0_Filter
FBB1 2
3
GND GND
GND AGND
J22 FB_B2_S
J20
2 1 1
VOUT_LDO_LS1 VOUT_LDO_LS1
FBB2
4 3 2
6 5 3
VOUT_1V2_Filter VOUT_1V2_Filter
GND AGND
GND GND
J23 FB_B3_S
1
FBB3
2
3
GND AGND
SNVU851 – NOVEMBER 2023
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J29
J24