Advertisement
Quick Links
This configuration guide is designed to help one understand how to use a micro-controller unit (MCU) to
configure an LP8752x-Q1 PMIC. Instead of requiring a new one time programmable configuration (OTP)
for each design, a specific LP8752x-Q1 variants described in this configuration guide can be configured at
2
startup through I
C bus to meet design requirements.
...................................................................................................................
1
..........................................................................................................................
2
3
1
Typical MCU Connection to LP8752x-Q1 for Start-Up Configuration
2
3
4
Startup and Shutdown Sequence Timing Diagram
1
BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings
2
EN, CLKIN and GPIO Pin Settings
3
PGOOD OTP Settings
4
Protections OTP Settings
5
Device Identification and I
6
Interrupt Mask Settings
7
Regulator Control Settings Registers
Trademarks
All trademarks are the property of their respective owners.
SNVU596 - October 2018
Submit Documentation Feedback
LP8752x-Q1 Configuration Guide
.................................................................................................................
..................................................................................
....................................................................................
........................................................................................
......................................................................................................
...................................................................................................
.....................................................................................
2
C Settings
.....................................................................................................
.....................................................................................
Copyright © 2018, Texas Instruments Incorporated
Contents
List of Figures
.................................................
....................................................................
List of Tables
........................................................................
User's Guide
SNVU596 - October 2018
LP8752x-Q1 Configuration Guide
2
2
3
2
4
4
11
5
7
7
8
8
8
9
1
Advertisement
Related Manuals for Texas Instruments LP8752 Q1 Series
Summary of Contents for Texas Instruments LP8752 Q1 Series
-
Page 1: Table Of Contents
Device Identification and I C Settings ..................... Interrupt Mask Settings ..................Regulator Control Settings Registers Trademarks All trademarks are the property of their respective owners. SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 2: Introduction
Processor GPIOx PGOOD Copyright © 2018, Texas Instruments Incorporated Figure 1. Typical MCU Connection to LP8752x-Q1 for Start-Up Configuration SCL/SDA Pins The SCL and SDA lines (pins 5 & 6, respectively) are used to communicate between the MCU and the LP8752x-Q1 PMIC using an I C compatible Interface. -
Page 3: Configuration
3. Wait for nINT line to be set low. (Check RESET_REG bit, and set ENx pin low if necessary ) 4. Set new configuration using I C communication in recommended order. See Section 3.3 1. Voltage settings SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 4: Configuration Sequence During Startup
MCU configures device with a Register reset series of I C writes interrupt disables clears Enables PMIC interrupt PMIC Figure 3. Configuration Sequence During Reset LP8752x-Q1 Configuration Guide SNVU596 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 5 Peak current limit LP875230 3.5A LP875240 2A LP875250 3.5A Slew rate SLEW_RATE1 3.8 mV/µs Startup Delay BUCK1_STARTUP_DELAY 0 ms Shutdown Delay BUCK1_SHUTDOWN_DELAY 0 ms SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 6 Peak current limit LP875230 3.5A LP875240 3A LP875250 3.5A Slew rate SLEW_RATE3 3.8 mV/µs Startup Delay BUCK3_STARTUP_DELAY 0 ms Shutdown Delay BUCK3_SHUTDOWN_DELAY 0 ms LP8752x-Q1 Configuration Guide SNVU596 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 7 PGOOD output mode (push-pull or open PGOOD_OD drain) Active high (power PGOOD polarity (active high / active low) PGOOD_POL valid) SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 8 Masked level BUCK2 Buck2 current limit triggered BUCK2_ILIM_MASK Masked Buck3 PGOOD has reached threshold BUCK3_PG_MASK Masked level BUCK3 Buck3 current limit triggered BUCK3_ILIM_MASK Masked LP8752x-Q1 Configuration Guide SNVU596 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 9 SLEW_RATE1[1:0] EN_ROOF_FLOOR2, EN_RDIS2, BUCK2_EN_PIN _CTRL, EN_BUCK2, BUCK2_CTRL_1 BUCK2_FPWM, BUCK2_FPWM_MP BUCK_2_EN_PIN_SELECT[1:0] BUCK2 BUCK2_CTRL_2 SLEW_RATE2[1:0] EN_ROOF_FLOOR3, EN_RDIS3, BUCK3_EN_PIN _CTRL, EN_BUCK3, BUCK3_CTRL_1 BUCK3_FPWM BUCK_3_EN_PIN_SELECT[1:0] BUCK3 BUCK3_CTRL_2 SLEW_RATE3[1:0] SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 10 PGOOD events, regulator short-circuit events, and clock events. The registers containing all of these interrupts are listed as follows: • INT_TOP1 register • INT_TOP2 register • INT_BUCK_0_1 register • INT_BUCK_2_3 register LP8752x-Q1 Configuration Guide SNVU596 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 11 Once all of the other device settings have been set, the EN_PIN_CTRLx bit should be set high for each output that needs to be turned on for the design, allowing the ENx pin(s) to control each desired output. SNVU596 – October 2018 LP8752x-Q1 Configuration Guide Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 12 C commands and can move on to clearing interrupts and setting the ENx pin high to start startup sequence as described in Section 3.1. LP8752x-Q1 Configuration Guide SNVU596 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 13 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
- Page 14 FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
- Page 15 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 2. 実験局の免許を取得後ご使用いただく。 3. 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/ /www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 3.4 European Union 3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a low-voltage power-supply network that supplies buildings used for domestic purposes.
- Page 16 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated...
- Page 17 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated...
Need help?
Do you have a question about the LP8752 Q1 Series and is the answer not in the manual?
Questions and answers