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(3)
Example of UART mode setting
Setting bit
M0, M1
CK0, CK1, OSC0, OSC1
MASTER
POL
NchS
SIS
STPS
SWENA
MSB
SOS
STA0~3
STP0~3
PSEL, SIO
Receiving (RX)
受信 RX
（
）
Maximum tsck/8
最大tsck/8
tsck
送信 TX
（
）
SO9=1
SO0 SO1
Sending (TX)
STP=1 execution
STP=1実行
TSTA1=1実行
TSTA1=1 execution
シリアル出力
Serial output
カウンタ
９
０
counter
（
OTC0 OTC3)
～
(OTC0 to OTC3)
シリアル入力
Serial input
カウンタ
９
counter
(ITC0 to ITC3)
（
ITC0 ITC3)
～
BUSY1
RX F/F
Note:
When a pulse width of tsck/4 or below is inputted during receiving (RX), the start of receiving will
be cancelled.
Note:
The UART circuit has a data judgment circuit. When receiving starts, the data judgment circuit
outputs a 3-pulse data judgment pulse in the data position to judge the RX pin state. When at
least two of these pulses record the same data, the received data is read as the serial data
input. In other words, if noise occurs in one pulse in the pulse output position, the data can be
received normally.
Note:
This example shows sending and receiving without parity. The SO8 bit output is outptted as the
stop bit. In the specification with parity, the SO8/SI8 bits can be assigned to parity. However, if
transmission (TX) starts immediately after the issue of interruption, the stop bit width cannot be
secured. In this case, after the interruption is issued, allow the operation to wait for a stop bit
width or more before sending is executed.
Note:
UART of this product supports the full/duplex specification. If sending and receiving operations
are executed at the same time, they can be carried out normally. However, interruption is issued
when either operation is completed and the BUSY1 bit becomes "0". Determine receiving
operation using the RX F/F bit.
UART setting (M0 = 0, M1 = 1)
Transmission rate setting
Master setting (MASTER = 0)
Serial clock stop state = H 、
Data output at the falling edge and data input at the rising edge (POL = 0)
N-ch open drain setting (NchS = 1)
Setting of serial data pin to RX pin (SIS = 0)
Setting of stop condition to input counter (STPS = 1)
Stop weight disabled (SWENA = 0)
Output beginning with the least significant bit (MSB = 0)
Data output (SOS = 1)
Serial input/output start data: 0h
Serial input/output stop data: 9h
Select N-ch open-drain pin (TX2, RX2) (PSEL = 1, SIO = 1)
SO6 SO7 SO8
SO9
=1
=1
送信(TX)
Sending (TX)
割り込み発行
Issue of interruption
１
６
７
８
９
Receiving (RX)
受信 RX
（
）
データ判定パルス
Data judgment pulse
85
Condition setting data
tsck
SI0
SI1
SI5
SI6
受信(RX)
Receiving (RX)
Pulse widths of tsck/4 or below is not considered as received
tsck/4以下のパルス幅は受信と判断しません
。
０
１
６
tsck
SI0
SI1
TC9349AFG
F/F Reset=1
Issue of interruption
割り込み発行
７
８
９
2006-02-24
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