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5. IF Counter Configuration
The IF counter is composed of an input amplifier, a gate time control circuit and a 20-bit binary counter. The OSCin
prescaler clock can be inputted as the IF counter input.
TA2/3
IFin
IFin
49
0.01 µ F
V PLL
50
OSCin
Amplifi
51
0.01 µ F
TA0/1
Note: All the binary counters of the IF counter operate at the rising edge.
Note: When the OSCin prescaler clock is counted by the IF counter, 1/15･16 is fixed to the 1/16 frequency
division by setting the PLL mode to HF mode. The clock is directly inputted when in LF mode.
Note: The IF counter input amplifier, the OSCin input amplifier and the programmable counter are powered by
the V
pin power supply. This power supply level can be supplied regardless of the V
PLL
power supply level. In PLL off mode, the V
register and the IF counter power supply use the V
register will be retained after the V
Note: The IFin pin has a built-in amplifier that allows small-amplitude operation by linking to the capacitor. In
PLL off mode, the IFin input becomes high impedance.
IF counter input
Data set to
bit
STA/
STP
BUSY bit
1 kHz
Gate
Binary counter input
Example of operation timing in automatic IF counter mode
Note: The IF counter ues the 1 kHz clock. There is a delay of up to 1 ms from the time when the start
instruction is executed to the time when the gate opens.
Prescaler IN
Noise
Cancel
Gate
NC
1 kHz
PSC
1/15 ･ 16
HF
Prescaler
IN
pin power supply can be turned off. The IF counter control
PLL
CPU
pin power supply is turned off.
PLL
"1"
120
F0~F19
20-bit binary counter
OVER
Manual
Gate time
G0
control circuit
G1
To programmable counter
pin power supply. Therefore, the contents of the
TC9349AFG
OVER
STA/STP
/V
pin
DD
CPU
2006-02-24
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