Toshiba TC9349AFG Manual page 25

Cmos digital integrated circuit silicon monolithic
Table of Contents

Advertisement

I/O Map
(IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
φL1
Page 1
OUT1
Y1
Y2
Y4
Y8
Data port 1
0
Data port 2
1
Data port 3
2
Data port 4
3
Data port 5
4
Data port 6
5
Data port 7
6
LCD driver control
7
DISP OFF
LCD OFF
BIAS
*
G-register 1
8
G0
G1
G2
G3
G-register 2
9
G4
*
*
*
Data select
A
S1
S2
S4
S8
B
CA flag
*
*
*
Data-register 1 (DATA)
C
d0
d1
d2
d3
Data-register 2 (DATA)
D
d4
d5
d6
d7
Data-register 3 (DATA)
E
d8
d9
d10
d11
Data-register 4 (DATA)
F
d12
d13
d14
d15
Refer to the next page
φL2
OUT2
Y1
Y2
Y4
Y8
Y1
Interrupt enable flag
EF1
EF2
EF3
EF4
(INTR1)
(INTR2/TM)
(SIO/TP/W)
(TIMER)
Interrupt latch reset
ILR1
ILR2
ILR3
ILR4
(INTR1)
(INTR2/TM)
(SIOTP/W)
(TIMER)
INTR1 control
INTR2 control
POS1
NEG1
POS2
NEG2
-0
A/D converter control
AS SEL0
AS SEL1
AS SEL2
STA
-0
DO1 control
R0
R1
M0
M1
-0
DO2 control 1
R0
R1
M0
M1
-0
DO2 control 2
AUTO1
ENA
CK0
CK1
UNLOCK
PN
POL
LPFON
RESET
-0
MUTE control
MUTE
MUTE
POL
Break
ENA
Timer port interrupt
Timer reset
control
2 Hz F/F
Clock
CK SEL
ENA
-0
Pulse counter control 1
POS
NEG
DOWN
-0
*
Pulse counter control 2
CTR
OVER
-0
*
*
RESET
RESET
Timer counter control
CR
CK
PW
CR
-0
Disable
Timer counter interrupt detect data 1
ID0
ID1
ID2
ID3
Timer counter interrupt detect data 2
ID4
ID5
ID6
ID7
-0
φL3
φK1
OUT3
IN1
Y2
Y4
Y8
Y1
Y2
Data port 1
Data port 2
I/O port 3 output data
IF data 1
-1
-2
-3
F0
F1
I/O port 4 output data
IF data 2
-1
-2
-3
F4
F5
I/O port 5 output data
IF data 3
-1
-2
-3
F8
F9
I/O port 6 output data
IF data 4
-1
-2
-3
F12
F13
IF data 5
F16
F17
I/O port 8 output data
IF monitor
-1
-2
-3
Busy
MANUAL
G-register 1
G0
G1
G-register 2
G4
0
I/O port 3 control
Data select
-1
-2
-3
SEL1
SEL2
I/O port 4 control
CA flag
0
-1
-2
-3
I/O port 5 control
Data-register 1 (DATA)
-1
-2
-3
d0
d1
I/O port 16 control
Data-register 2 (DATA)
-1
-2
-3
d4
d5
Data-register 3 (DATA)
d8
d9
I/O port 16 data
Data-register 4 (DATA)
-1
-2
-3
d12
d13
25
φK2
IN2
Y4
Y8
Y1
Y2
Y4
Interrupt enable flag
EF1
EF2
EF3
(INTR1)
(INTR2/TM)
(SIO)
Interrupt latch
ILR1
ILR2
ILR3
(INTR1)
(INTR2/TM)
(SIOTP/W)
Interrupt master flag
F2
F3
IMF
0
0
A/D converter data
F6
F7
AD0
AD1
AD2
A/D converter data
F10
F11
AD4
AD5
Busy
F14
F15
STOP
BUZER
VDO OFF
F/F
10 Hz
F/F
F18
F19
Unlock detect
OVER
0
UNLOCK
ENA
Unknown
MUTE control
MUTE
G2
G3
IO1
POL
0
0
Timer
SEL4
SEL8
2 Hz F/F
10 Hz
100 Hz
Pulse counter data
0
0
PC0
PC1
PC2
Pulse counter data
d2
d3
PC4
PC5
PC6
Pulse counter data
d6
d7
OVER
0
0
Timer counter data 1
d10
d11
CT0
CT1
CT2
Timer counter data 2
d14
d15
CT4
CT5
CT6
TC9349AFG
φK3
IN3
Y8
Y1
Y2
Y4
Y8
EF4
(TIMER)
ILR4
(TIMER)
I/O port 3 input data
0
-0
-1
-2
-3
I/O port 4 input data
AD3
-0
-1
-2
-3
I/O port 5 input data
0
-0
-1
-2
-3
I/O port 6 input data
-0
-1
-2
-3
0
I/O port 8 input data
Unknown
-0
-1
-2
-3
I/O port 9 input data
IN
0
-0
-1
-2
I/O port 10 input data
-0
-1
-2
-3
200 Hz
I/O port 12 input data
PC3
-0
-1
-2
-3
I/O port 13 input data
PC7
-0
-1
-2
-3
I/O port 14 input data
0
-0
-1
-2
-3
I/O port 15 input data
0
0
CT3
-0
-1
I/O port 16 input data
CT7
-0
-1
-2
-3
2006-02-24

Advertisement

Table of Contents
loading

Table of Contents