Toshiba TC9349AFG Manual page 101

4. Programmable Counter Circuit Configuration
The circuit consists of an amplifier, 1/15･16 2-modulus pre-scaler, a 4-bit swallow counter and a 12-bit binary
programmable counter. When the HF mode is selected, the 1/15･16 pre-scaler, the 4-bit swallow counter and the 12-bit
binary programmable counter are used. When the LF mode is selected, only the 12-bit binary programmable counter is
used.
The OSCin input clock is supplied to the DC-DC converter for VT, and used as the doubler clock. The clock divided
by the programmable counter is also supplied to the phase comparator and the IF counter.
( → Refer to the sections on DC-DC converter for VT and Phase comparator.)
TA0, TA1
VPLL
50
OSCin
Amplifier
51
0.01 µF
To DC-DC converter for VT
Note: The programmable counter uses the V
regardless of the power supply level of the V
supply can be turned off. The programmable counter setting registers use the V
that the contents of the registers are retained after the V
Note: The OSCin pin has an amplifier that allows small-amplitude operation with coupled capacitor. The OSCin
input is subject to high impedance in the PLL off mode.
1/16
HF
1/15･16
HF
1/15
LF
To phase comparator
To IF counter
pin power supply. This power supply can be supplied
PLL
/V
DD CPU
101
P0~P3
4-bit
swallow counter
Preset
12-bit
programmable counter
P4~P15
pin. In the PLL off mode, the V
CPU
pin power supply is turned off.
PLL
TC9349AFG
To phase comparator
pin power
PLL
pin power supply, so
2006-02-24