Toshiba TC9349AFG Manual page 110

Control 3 for DC-DC converter for VT VT 用 DC-DC コンバータコントロール
Y1 Y2 Y4
DDCK DDCK
φL15(7)
POL
SEL ENA
The DC-DC converter for VT outputs the double clock using the DDCK1 (also used as pin P8-1) or the DDCK2 (also
used as pin P9-2). Setting the DDCK ENA bit to "1" enables the doubler operation. The DDCK SEL bit is used to select the
pin to be used.
The clamp function is provided to keep the doubled voltage at or below a certain voltage. The clamp is controlled by the
doubler detection voltage pin VDET (also used as pin P8-1). The doubled voltage is divided by resistance and the resultant
potential is inputted into the VDET pin. When the VDET pin potential becomes lower than 0.75 V or 1.00 V, the doubler
clock will operate. When the potential becomes higher than these values, the doubler clock will be stopped. The detection
voltage can be selected from 0.75 V and 1.00 V and the detection operation is enabled by setting the VDET ENA bit to "1".
The doubler clock can be selected from 15 types. Select a frequency that is a little influence by the tuner beat or other
factors.
The control port for the DC-DC converter for VT is assigned to data port 5, and is accessed by using the OUT1
instruction with [CN = 4H] specified in the operand. These control bits are reset to "0" after system reset.
Note: Set the Y2 bit of the Control 1 for the DC-DC converter for VT ( φ L15 (5)) to "0".
Note: When the doubler clock pin (DDCK1/2) and the doubler detection voltage input (VDET) are selected, the
I/O port output data and control data of the same pins will be in "don't care" state.
Note: The DC-DC converter detection voltage input (VDET ENA bit) must be disabled ("0") in the PLL off mode
or when it is not being used; otherwise it will increase the consumption current.
３
Y8
*
Clock output logic setting
クロック出力論理設定
Permission of clock output クロック出力の許可
Selection of clock output pin
クロック出力端子の選択
110
0: Negative logic "H" or "HZ" output when the output is
0：負論理...出力停止時"H"または"HZ"出力
stopped
1：正論理...出力停止時"L"出力
1: Positive logic "L" output when the output is stopped
0: Prohibition (I/O port function) 0：禁止 (I/O ポート機能)
1：許可 (DC-DC コンバータ出力機能)
1: Enabled (DC-DC converter output function)
0: Use the DDCK1 pin (internal N-ch transistor)
0：DDCK1 端子 (内部 Nch トランジスタ) を使用
1: Use the DDCK2 pin (external transistor)
1：DDCK2 端子 (外部トランジスタ) を使用
TC9349AFG
2006-02-24