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Block Diagram
V
DD
P8-0/VDET (BRK13)
P8-1/SI2/DDCK1 (BRK14)
P8-2/SCK2/RX2 (BRK15)
P8-3/SDIO2/TX2 (BRK16)
DDCK1
V
CPU
DDCK2 MUTE
P9-0/Tout
MUTE/P9-1
P9-2/DDCK2/TEST
V
DD
IFin/IN
V
PLL
OSCin
GND
DO1/OT1/P
DO2/OT2/NTin
RESET
GND
Xin1
Xout1
VDD
C1
C2
V
DB
V
EE
C3
C4
V
LCD
: N-ch Open drain
MUTE
G-Reg.
MUTE
V
LCD
RAM
(4 × 512 Words)
Port 8
Interrupt Stack Reg.
(4 Levels)
VDET
Data
DDCK
DDCK
Select
Control
V
Data Reg (16 bits)
EE
V
DB
Port 9
ROM
(16 × 8192 Steps)
V
LCD
IF
Counter
DDCK
Program
Counter
PLL
Address Stack Reg.
(16 Levels)
Phase
Comp.
VDB
Reset
OSC
Reset
Control
OSC2
OSC1
Peripheral
Doubler
V
EE
(1.5 V)
LCD
Port 10 Port 12 Port 13
Driver
V
LCD
Doubler
V
DB
R/WBuf.
ALU
Ca
Instruction
Decoder
BUZR
Interrupt
Control
V
DB
Timer
Up/Down
Counter
Serial
Interface
CPU
Clock
OSC2
Port 14
Port 15
4
TC9349AFG
V
V
DD
LCD
P6-3/ADin4 (BRK12)
P6-2/ADin3 (BRK11)
Port 6
P6-1/ADin4 (BRK10)
P6-0/ADin4 (BRK9)
A/D
Conv.
V
V
EE
DB
V
LCD
VR
P5-3/VRout2
P5-2/VRin2
Port 5
P5-1/VRcom
P5-0/VRin1
P4-3/VRout1 (BRK8)
P4-2/BUZR (BRL7)
Port 4
P4-1/INTR2/ INH (BRK6)
P4-0/INTR1 (BRK5)
V
V
DD
LCD
V
V
DD
LCD
P3-3/PCTRin (BRK4)
P3-2/S11 (BRL3)
Port 3
P3-1/SDIO/TX1 (BRK2)
P3-0/SCK1/RX1 (BRK1)
V
DD
OSC2
V
DD
Port 16
V
LCD
2006-02-24
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