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Exercise particular care regarding the following points when using multiplex interrupt:
1)
The priority of the interrupt factors
2)
Restrictions on the address stack levels used when interrupt requests are issued.
3)
Shunting processing for the carry flag, data memory, etc.
(1)
Priority of interrupt factor
The order of priority for multiplex interrupt becomes A < B < C < D as shown in the figure.
When an order of priority of this type applies, the processing of interrupt C must have priority during the interrupt
processing of A or B, while the processing of interrupt D is in turn given priority during execution of interrupts C.
Multiplex interrupt requires the setting of priority levels. For example, for interrupt factors A and B, let us assume
that a request is issued for factor A every 10 ms, with an interrupt processing time of 4 ms; and that a request is issued
for factor B every 2 ms, with an interrupt processing time of 1 ms. When there is no order of priority for A and B,
then, should an A interrupt request occur during the interrupt processing of B, it may sometimes be the case that the A
interrupt processing is executed and the B interrupt processing is not. In such a case, it is necessary to set the order of
priority of A < B through programming and prohibit any A interrupt during interrupt processing of B, and also allow a
B interrupt to be received even during the interrupt processing of A.
Priority ordering of this kind is set through the priority level ports (φL14(6), φL14(7)), described in the item on the
interrupt priority circuit block. Setting interrupt priority in the order of factors A < B < C < D prohibits during the
processing of a prioritized interrupt any interrupt with the same priority level or lower. For example, all interrupts are
prohibited during factor D interrupt, while during processing of a factor C interrupt, factor D interrupt is enabled
while factor A, B and C interrupts are prohibited. Any change in the interrupt order is prohibited during the
processing of an interrupt. To prohibit the acceptance of a higher-priority interrupt factor during the execution of a
lower-priority interrupt, use a DI/EI instruction to prohibit interrupt in the program area where prohibition is required.
(2)
Restriction of address stack levels
As described in the section on interrupt reception processing, when an interrupt request is issued, the return address
is automatically evacuated to the address stack register; and the G-register, data selection, carry flag and data register
are automatically evacuated to the interrupt stack register. There are four interrupt stack levels and 16 address stack
levels. The content of the interrupt stack register and the address stack register is broken when the interrupt stack
levels and the address stack levels are exceeded; it is therefore necessary to use them in such a way to ensure they are
not exceeded. Since it can also be used with the execution of a subroutine call command, the address stack register
should take into account the address stack levels for both interrupt and subroutine calls.
(3)
Evacuation processing
When using multiplex interrupt, it is necessary to secure the evacuation area for evacuation processing separately
for each Interrupt factor.
53
TC9349AFG
2006-02-24
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