Toshiba TC9349AFG Manual page 34

Backup mode
Backup mode decreases the operating current and holds data memory and other registers. Backup mode can be
implemented through programming-based backup or hardware-based backup.
For programming-based backup, three types of backup mode are possible through the executing of CKSTP or WAIT
instructions.
For hardware-based backup there are two types of function: a decreased voltage detection function and a power-off
backup function. When the V
1.225 V), a decrease voltage detection function stops the CPU temporarily and prevents incorrect operation of the CPU.
During this time, the operational status of such items as the LCD driver, I/O ports, and PLL is held. If the V
set to approximately 0.5 V or less, the power-off backup function will stop functions such as LCD driver, I/O port, and PLL
operations; reduce the only power supply for the CPU (V
memory contents and the status of other registers.
1. Clock stop mode
Execution of the CKSTP instruction actuates clock stop mode.
Clock stop mode suspends system operations while maintaining the internal status immediately prior to suspension. At
this time, the V , V
DD PLL and
oscillation stops; the LCD indication output pin and CMOS output port are fixed to the "L" level; and the N-ch open drain
pins are all set to the OFF (high-impedance) state automatically. The power supply of the V
lowered to the OFF state, and the power supply of the V
Clock stop is released under the following conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) If the V power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the VDD
DD
power supply break is enabled (BRAEK ENA bit (φL11(F)) = "1").
Release of clock stop mode causes the next address to be executed after 100 ms of standby time have elapsed.
Note: The PLL changes to the off state during execution of the CKSTP instruction.
Break pin
X pin
OUT1
CPU
operation
CKSTP
instruction
Example of Operation Timing Using a Break Pin
Note: Clock stop mode is actuated on execution of the CKSTP instruction.
Note: When break pin input is set, it is necessary to read this input state before execution of the CKSTP
instruction.
pin power supply falls to the decreased voltage detection setting potential (V
DD
CPU
pin power supplies change to low consumption current (10 or less µA); crystal
V
CPU
CPU
High impedance
Clock stop
(about 100 ms)
Executing of
CKSTP instruction
34
pin) to a low consumption current (0.5 µA or less); and hold
pin power supply can be lowered to 0.75 V.
CPU
Standby
operation
TC9349AFG
= 0.85 V -
DD
pin level is
DD
and V pins can be
DD PLL
Executing of
CKSTP instruction
2006-02-24