Toshiba TC9349AFG Manual page 82

(6) Serial operation monitor
BUSY1/BUSY2 bits (Operation monitor)
The BUSY1/BUSY2 bits detect the serial operating state. The BUSY1 bit can detect the serial clock operating state,
while the BUSY2 bit can detect the operating state in the 2-wire mode or the receiving operation state in the UART
mode. When interruption is enabled, it will be issued at the falling edge of the BUSY1 bit and the program will
branch to address 0001H.
SOERR bit (2-wire serial output error flag)
The SOERR bit is used to detect arbitration in the 2-wire multi master mode. When serial data is outputted in the
master mode, the output state is compared to the internal output data. If there is any discrepancy between them, the
serial operation will be stopped automatically and the SOERR bit set to "1". When this state is detected, the serial
clock and data respectively will be opened and the operation will continue. For normal arbitration detection, the serial
operation will be stopped by the clock supplied from another master. When the 2-wire operation is completed, FF
Reset = "1" will be set and the flag will be reset.
This detection is carried out during serial output setting, regardless of the master or slave mode. Therefore, program
processing is required if any discrepancy occurs in the output data due to noise or for any other reason. Usually,
provide a timer to detect this bit if there is no issue involving interruption or the BUSY1 signal does revert to "L"
after a certain time has elapsed. If the detected bit is "1", set the STP bit to "1" to execute stop and initialization.
In any other modes than the 2-wire mode, this bit is in the "don't care" state.
シリアルクロック
Serial clock
（ SCK)
(SCK)
Serial input/output
シリアル入出力
(SDIO)
（ SDIO)
SOERRビット
SOERR bit
RX F/F bit (Receiving flag)
The RX F/F bit detects the receiving of UART or the 3-wire slave. This bit is effective only in slave mode. When
the serial clock receives input or UART when in slave mode, this bit is set to "1". After receiving is completed, refer
to the received serial data. This bit is reset to "0" by setting the FF Reset bit to "1".
F/F Reset bit (Internal flag reset)
This bit initializes the internal flag. Each time this bit is set to "1", the internal flag will be reset.
Serial receiving execution flag (RX F/F), the serial data output error detection flag in the 2-wire mode, and the
serial wait are reset and released.
In the 2-wire mode, the system will enter the wait state after output of the serial output data SOF bit. Usually, the
SOF/SIF bits are used as the acknowledgement of (ACK) bits. After reading the ACK bit input/output, serial
operation will be restarted by execution of the F/F Reset bit.
Internal flag reset (F/F Reset bit)
→ "The internal flag is reset each time this flag is set to "1".
The wait state is released in the 2-wire mode.
Start and stop operation timing in the 2-wire mode
２ 線式設定時の開始・停止動作タイミング
ストップ
Stop Start
コンディション コンディション
condition condition
Serial clock
シリアルクロック
(SCK)
（ SCK)
シリアル入出力
Serial input/output
(SDIO) （ SDIO)
Execution of
命令の実行
instruction
STP="1"実行 TSTA1="1"実行
STP= "1" execution TSTA= "1" execution
シリアル出力
Serial output
カウンタ E
counter
（ OTC0 OTC3) ～
(OTC0 to OTC3)
シリアル入力
Serial input counter
カウンタ E
(ITC0 to ITC3)
（ ITC0 ITC3) ～
スタート
F/F Reset="1"実行
F/F Reset= "1" execution
７ ６ ０
７ ６ ５ ０
82
２ 線式のとき シリアルクロック 、
In the 2-wire mode, the serial
およびシリアル出力端子は開
clock and the serial output
放されます pin are opened. 。
シリアルデータ異常
Serial data error
（ ACK ）
TSTA2= "1" execution
TSTA2="1"実行
F ７ ６
F ７ ６ ５ ０
TC9349AFG
ストップ
Stop
コンディション condition
（ ACK ）
STP= "1" execution
STP="1"実行
F/F Reset="1"実行
F/F Reset= "1" execution
０ F E
F E
2006-02-24