Part 2.5: Usb To Serial Port - Alinx KINTEX UltraScale FPGA AXKU042 User Manual

KINTEX UltraScale+ FPGA Board AXKU042 User Manual
The Gigabit Ethernet interface pin assignments are as follows:
Signal Name FPGA Pin Name
PHY_GTXC B48_L21_N
PHY_TXD0 B48_L18_N
PHY_TXD1 B48_L18_P
PHY_TXD2 B48_L23_N
PHY_TXD3 B48_L23_P
PHY_TXEN B48_L21_P
PHY_RXC B48_L12_P
PHY_RXD3 B48_L17_N
PHY_RXD2 B48_L17_P
PHY_RXD1 B48_L15_N
PHY_RXD0 B48_L15_P
PHY_RXDV B48_L12_N
PHY_MDC B48_T2U
PHY_MDIO B48_T1U
PHY_RESET B48_T3U

Part 2.5: USB to Serial Port

The AXKU042 FPGA development board is equipped with a Uart to USB interface
for serial communication and debugging of the development board. The conversion
chip uses the USB-UAR chip of Silicon Labs CP2102GM. The CP2102 serial chip and
the FPGA are connected by a level-shifting chip to adapt to different FPGA BANK
voltages. The USB interface uses the MINI USB interface, which can be connected to
the USB port of the upper PC for serial data communication on the FPGA
development board with a USB cable. The schematic diagram of the USB Uart circuit
design is shown below in table 6-1:
www.alinx.com
Figure 2-4-1 schematic diagram
Pin No.
W34 Ethernet 1 Transmit Clock
AD33 Ethernet 1 Transmit Data bit０
AC33 Ethernet 1 Transmit Data bit1
V34 Ethernet 1 Transmit Data bit2
U34 Ethernet 1 Transmit Data bit3
V33 Ethernet 1 Transmit Enable Signal
AC31 Ethernet 1 Receive Clock
AB34 Ethernet 1 Receive Data Bit0
AA34 Ethernet 1 Receive Data Bit1
AD34 Ethernet 1 Receive Data Bit2
AC34 Ethernet 1 Receive Data Bit3
AC32 Ethernet 1 Receive Enable Signal
AA33 Ethernet 1MDIO Management Clock
AE31 Ethernet 1MDIO Management Data
V32 Ethernet Chip Reset
Description
32 / 49