Part 1.5: Clock Configuration - Alinx KINTEX UltraScale FPGA AXKU042 User Manual

KINTEX UltraScale+ FPGA Board AXKU042 User Manual
Signal Name
QSPI_CCLK
QSPI0_CS_B
QSPI0_IO0
QSPI0_IO1
QSPI0_IO2
QSPI0_IO3
Signal Name
QSPI_CCLK
QSPI1_CS_B
QSPI1_IO0
QSPI1_IO1
QSPI1_IO2
QSPI1_IO3

Part 1.5: Clock configuration

200Mhz differential clock source
A differential 200MHz clock source is provided on the FPGA development board
to provide the system clock to the FPGA. The crystal differential output is connected
to the FPGA BANK45, which can be used to drive the DDR controller operating clock
and other user logic in the FPGA. The schematic diagram of the clock source is shown
in Figure 1-5-1.
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FPGA
Pin Name
CCLK_0
RDWR_FCS_B_0
D00_MOSI_0
D01_DIN_0
D02_0
D03_0
FPGA
Pin Name
CCLK_0
IO_L2N_T0L_N3_FWE_FCS2_B_65
IO_L22P_T3U_N6_DBC_AD0P_D04_65
IO_L22N_T3U_N7_DBC_AD0N_D05_65
IO_L21P_T3L_N4_AD8P_D06_65
IO_L21N_T3L_N5_AD8N_D07_65
Figure 1-5-1
FPGA
Pin
AA9
U7
AC7
AB7
AA7
Y7
FPGA
Pin
AA9
G26
M20
L20
R21
R22
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