Part 2.4: Gigabit Ethernet Interface - Alinx KINTEX UltraScale FPGA AXKU042 User Manual

SFP2_TX_N
SFP2_RX_P
SFP2_RX_N
SFP2_TX_DIS
SFP2_LOSS

Part 2.4: Gigabit Ethernet Interface

There are 1 Gigabit Ethernet port on the AXKU042 FPGA Development board. The
GPHY chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide users with
network communication services.The KSZ9031RNX chip supports 10/100/1000 Mbps
network transmission rate, and communicates with the MAC layer of the system
through the RGMII interface. KSZ9031RNX supports MDI/MDX adaptation, various
speed adaptation, Master/Slave adaptation, and supports MDIO bus for PHY register
management.
When the KSZ9031RNX is powered on, it will detect the level status of some
specific IOs to determine its own operating mode. Table 3-5-1 describes the default
settings after the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data transmission
FPGA chip and PHY chip KSZ9031RNX is communicated through the RGMII bus, the
transmission clock is 125Mhz, and the data is sampled on the rising edge and falling
samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of FPGA
chip and PHY chip KSZ9031RNX is communicated through RMII bus, and the
transmission clock is 25Mhz. Data is sampled on the rising edge and falling samples
of the clock.
Ethernet PHY chip connection diagram as shown in Figure 2-4-1:
KINTEX UltraScale+ FPGA Board AXKU042User Manual
W3 SFP Optical Module Data Transmit Negative
V2 SFP Optical Module Data Transmit Positive
V1 SFP Optical Module Data Transmit Negative
AM11 SFP optical module transfer Disable, active high
AN9 SFP light optical LOSS,High level means no light signal is received
Description
MDIO/MDC mode PHY Address
Enable 125Mhz clock output selection
LED light mode configuration
Link adaptation and
configuration
Configuration value
PHY Address 为 011
Enable
Single LED light mode
full duplex 10/100/1000 adaptive, compatible
with full-duplex, half-duplex
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