Sram Device; Limitations; Operating Voltage; Nor Flash Memory Device - ST STM32L4R9I User Manual

UM2248
6.20

SRAM device

IS61WV102416BLL, a 16-Mbit static RAM (SRAM), 1 M x 16 bit (U17), is installed on the
STM32L4R9I-EVAL main board. The STM32L4R9I-EVAL main board, as well as the
addressing capabilities of FMC, allow hosting SRAM devices up to 64 Mbytes. This is the
reason why the schematic diagram mentions several SRAM devices.
The SRAM device is attached to the 16-bit data bus and accessed with FMC. The base
address is 0x6000 0000, corresponding to NOR/SRAM1 bank1. The SRAM device is
selected with the FMC_NE1 chip selection. FMC_NBL0 and FMC_NBL1 signals allow the
selection of 8- and 16-bit data word operating modes.
By removal of R134, a zero-ohm resistor, the SRAM is deselected, and the STM32L4R9AII6
ports PD7, PE0, and PE1 corresponding to FMC_NE1, FMC_NBL0, and FMC_NBL1
signals, respectively, are usable for other application purposes.
.
Resistor
R134
6.20.1

Limitations

The SRAM addressable space is limited if some or all of the A21 FMC address lines are
shunted to the CN12 connector for debug trace purposes. In such a case, pull-down resistors
drive the disconnected addressing SRAM inputs.
associated configuration elements.
6.20.2

Operating voltage

The SRAM operating voltage is in the range of 2.4 to 3.6 V.
6.21

NOR flash memory device

M29W128GL70ZA6E, a 128-Mbit NOR flash memory, 8 M x16 bit (U11), is installed on the
STM32L4R9I-EVAL main board. The STM32L4R9I-EVAL main board, as well as the
addressing capabilities of FMC, allow hosting M29W256GL70ZA6E, a 256-Mbit NOR flash
memory device. This is the reason why the schematic diagram mentions both devices.
The NOR flash memory device is attached to the 16-bit data bus and accessed with FMC.
The base address is 0x6800 0000, corresponding to NOR/SRAM2 bank1. The NOR flash
memory device is selected with the FMC_NE3 chip select signal. A pull-up resistor
connected to the BYTE terminal of the NOR flash memory selects the 16-bit data word
Operating mode. The jumper (JP6) is dedicated to the write-protect configuration.
By default, the FMC_NWAIT signal is not routed to the RB port of the NOR flash memory
device, and, to know its ready status, its status register is polled by the demo software
installed in STM32L4R9I-EVAL. This is modifiable with configuration elements, as shown in
Table 16.

Table 15. SRAM chip select configuration

Fitting
ON Default setting: SRAM chip select is controlled with FMC_NE1
SRAM is deselected. FMC_NE1 is freed for other application
OFF
purposes.
UM2248 Rev 5
Hardware layout and configuration
Configuration
Section 6.4 provides information on the
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