Tr (Temporary Relay) Area; Cpu Bus Link Area - Omron SYSMAC CVM1 Series Operation Manual

CPU Bus Link Area

3-4

TR (Temporary Relay) Area

3-5

CPU Bus Link Area

Caution
!
SYSMAC BUS Area addresses range from CIO 2300 through CIO 2555. These
256 words are divided into 8 groups of 32 words each and are allocated to Mas-
ters according their number setting. The following table shows the default ad-
dress allocation.
RM # 0 1
CIO 2300 2332
words to to
2331 2363
Words are allocated to Units on Slave Racks in order beginning with the Slave
Rack with the lowest unit number. Up to 8 Slave Racks can be connected to each
Master. Word addresses are assigned to Units in the first Slave Rack in the order
in which they are mounted left to right. Word allocation then continues left to right
on the Slave Rack with the next lowest unit number, and so on until words have
been allocated to all of the Slave Racks.
Words are allocated to I/O Terminals and Optical I/O Units according to word set-
tings on the Unit. The word allocated is calculated by adding the first word of the
Master and the word setting on the Unit. To minimize the chance of overlapping
with words allocated to Slave Racks, it is recommended to set I/O Terminal and
Optical I/O Unit settings beginning from 31, the last word allocated to the Master,
and continuing down to lower settings.
Refer to the SYSMAC BUS Remote I/O System Manual for details on word al-
location to I/O Terminals and Slave Racks.
After the I/O Table has been registered or edited, an "I" will appear before input
bit addresses and a "Q" will appear before output bit addresses on SSS displays.
Refer to the SSS Operation Manuals for details on the PC Setup.
The TR Area provides eight bits that are used only with the LD and OUT instruc-
tions to enable certain types of branching ladder diagram programming. It is only
necessary to use TR bits when entering the program using mnemonic code. The
SSS enters TR bits automatically, although the TR bits are not shown on the
SSS screen. The use of TR bits is described in Section 4 Writing Programs.
TR addresses range from TR0 though TR7. Each of these bits can be used as
many times as required and in any order required as long as the same TR bit is
not used twice in the same instruction block.
The CPU Bus Link Area is indicated by a G prefix. Addresses range from G000
to G255. The CPU Bus Link Area can be divided into 3 sections, the PC Status
Area, Clock/Calendar Area, and Data Link Area.
G000 is the PC Status Area and contains flags and control bits relating to PC
status. G001 to G004 are the Clock/Calendar Area, and G005 to G007 are not
used.
Most of the CPU Bus Link Area (G008 to G255) is taken up by the Data Link Area
which is used to transfer information between CPU Bus Units and the CPU. CPU
Bus Units connect to the CPU bus on the CPU Rack or Expansion CPU Rack.
The CPU Bus Link Area words G000 through G007 cannot be written to from the
user program and can only be read from to access the data provided there.
2 3 4
2364 2396 2428
to to to
2395 2427 2459
Section 3-5
5 6 7
2460 2492 2524
to to to
2491 2523 2555
39