Omron CVM1D Operation Manual
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Omron CVM1D Operation Manual

Omron CVM1D Operation Manual

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Table of Contents

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This section provides general precautions for using the Programmable Controller (PC) and related devices.
The information contained in this section is important for the safe and reliable application of the Programmable Con-
troller. You must read this section and understand the information contained before attempting to set up or operate a
PC system.
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PRECAUTIONS
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  • Page 1: Table Of Contents

    PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the Programmable Con- troller. You must read this section and understand the information contained before attempting to set up or operate a PC system.

  • Page 2: Intended Audience

    It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applications.

  • Page 3: Operating Environment Precautions

    Application Precautions • Changing present values in memory from a Programming Device. • Force-setting/-resetting bits from a Programming Device. • Transferring I/O memory from a host computer or from another PC on a net- work. Caution Execute online edit only after confirming that no adverse effects will be caused by extending the cycle time.
  • Page 4 Insufficient safety measures against short-circuiting may result in burning. • Do not mount a CVM1D Power Supply Unit in a CVM1 or CV-series PC. Doing so may result in burning or malfunction. • Do not mount a CVM1 or CV-series Power Supply Unit on a Duplex CVM1D PC.

  • Page 5: Conformance To Ec Directives

    Always ensure that devices operating at voltages of 50 to 1,000 VAC and 75 to 1,500 VDC meet the required safety standards for the PC (EN61131-2). The CVM1D, CVM1, and CV-series PCs that comply with EC Directives must be installed as follows: 1, 2, 3...
  • Page 6 Countermeasures are required when the load switching frequency of the overall PC exceeds 5 times/minute. Refer to 3-8 Compliance with EC Directives in the CVM1D Installation Guide for examples of circuits that can be used to reduce noise generated by switching.
  • Page 7 It provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. It also describes the Programming Devices that can be used and provides a list of related FA products and manuals.

  • Page 8: Overview

    “How does the PC know when to activate each pusher?” Much more complicated operations are also possible. To achieve proper control, CVM1D PCs use a form of PC logic called ladder-dia- gram programming. A single ladder-diagram program is used, as in C-series PCs.

  • Page 9: Pc Terminology

    Appendix A Standard Models lists products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Although a Unit is any one of the building blocks that goes together to form a CV-series PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.

  • Page 10: Overview Of Pc Operation

    1. Determine what the controlled system must do, in what order, and at what times. 2. Determine what Racks and what Units will be required. Refer to the CVM1D PC Installation Guide. If a Link System is required, refer to the appropriate System Manual.

  • Page 11: Pc Operating Modes

    10. Test the program in an actual control situation and carry out fine tuning as required. Refer to the SSS operation manuals for details on debugging op- erations. (Refer to Section 6 Troubleshooting in the CVM1D PC Installation Guide.) 11. Record two copies of the finished program on masters and store them safely in different locations.

  • Page 12: Run Output

    • Transferring I/O memory from another PC or host computer in the network DEBUG Mode DEBUG mode cannot be used in CVM1D mode. DEBUG mode is used to check program execution and I/O operation after syn- tax errors in the program have been corrected. With SFC programs, step execu- tion or section operation can be used to check for errors from a Programming Device using the DEBUG operation.

  • Page 13: Programming Devices

    CVM1D PCs cannot be programmed. Furthermore, programs containing these AR Area words cannot be transferred. 2. Errors that have been added to the CVM1D (the duplex bus error, duplex verification error, and duplex power supply error) will not be displayed on Programming Consoles other than the CVM1-PRS21-EV1 version 2.0.

  • Page 14: Connecting Programming Devices

    1-7-4 Recommended Programming Device Operations Checking the PC Setup The CVM1D’s PC Setup settings can be changed with the SSS. The PC Setup settings are all set to their default values when the CPU Unit is shipped. Verify that the PC Setup settings are appropriate for the planned PC applications.

  • Page 15: Cvm1D Program Memory

    Program Memory is backed up by the CPU battery, so data will not be lost during a power interruption. Note The program memory chip is built into CVM1D PCs and does not need to be installed by the user. PC Setup This area of Program Memory contains the settings described in Section 7 PC Setup.
  • Page 16 Section 1-9 Related Manuals Product Model number Manual Cat. No. Temperature Controller Data CV500-TDL21 Temperature Controller Data Link Unit W244 Link Unit Operation Manual Personal Computer Unit CV500-VP213-E/ Personal Computer Unit Operation Manual W251 VP223-E/VP217-E/ VP223-E/VP217-E/ Personal Computer Unit Technical Manual W252 VP227-E Analog I/O Units...
  • Page 17 Hardware Considerations This section provides information on hardware aspects of CVM1D PCs that are relevant to programming and software opera- tion. These include switches on the CPU Unit and basic PC configuration. This information is covered in more detail in the CVM1D Installation Guide.
  • Page 18 CPU Unit Switch Settings There aren’t any special preparations required for the CPU Unit during program- ming, but the switch settings described in this section may be required before starting operation. CVM1D-CPU21 CPU Unit 1. Protect Keyswitch 3. EM Unit compartment 5.

  • Page 19: Cpu Unit Switch Settings

    Section 2-1 CPU Unit Switch Settings 1, 2, 3... 1. Protect Keyswitch Be sure that the Protect Keyswitch is set to NORMAL when transferring the program, writing the program, or changing the PC Setup. The program can- not be edited or transferred when the keyswitch is set to PROTECT. Position Function Memory is not write-protected.

  • Page 20: Duplex Unit Switch Settings

    Verify that the backup battery is installed before operating the PC. Duplex Unit Switch Settings Some Duplex Unit switch settings are required before programming and others are required before starting operation. CVM1D-DPL01 Duplex Unit 1. Left CPU Usage 1. Right CPU Switch Usage Switch 2.
  • Page 21 Section 2-2 Duplex Unit Switch Settings 1, 2, 3... 1. CPU Usage Switches These switches control the power supply to the left and right CPU Units. In a duplex system, set both CPU Usage Switches to “CPU USE.” In a simplex system, set the desired CPU Unit’s Usage Switch to “CPU USE”...
  • Page 22 Section 2-2 Duplex Unit Switch Settings 5. Peripheral Connector This connector is used to connect a Programming Device such as a comput- er running SSS or a Programming Console. The baud rate depends upon the Programming Device that is connected, so be sure to set the baud rate on the Communications DIP Switch.

  • Page 23: Em Units

    A511. A511 is in a read-only area, but the current bank number can be changed with the EMBC(171) instruction. Refer to Section 5 Instruction Set for details. Refer to the CVM1D Installation Guide for details on installing and removing EM Units.

  • Page 24: Memory Cards

    In a duplex system, the left and right CPU Units must have Memory Cards with the same capacity. The CVM1D does not support Memory Card instructions, but the program and other data can be transferred from the Memory Card to the CPU Unit automati- cally at start-up.

  • Page 25: File Transfer Between The Cpu And Memory Card

    Section 2-4 Memory Cards 4. Close the cover. Memory Card indicator Memory Card power switch Memory Card eject button Memory Card Cover Removing a Memory Card 1, 2, 3... 1. Open the cover of the Memory Card compartment. 2. Press the Memory Card power switch once if the Memory Card indicator is lit.
  • Page 26 Section 2-4 Memory Cards 2. The files that will be transferred at start-up must be named “AUTOEXEC.” 3. Files called BACKUP are created when the simplified backup function is used. Refer to 2-4-3 Simplified Backup Function for details. File Transfer at Start-up There are two methods for automatic transfer of files at start-up: 1, 2, 3...

  • Page 27: Simplified Backup Function

    Section 2-4 Memory Cards 2. Reading and writing can be performed by a command from a host computer. 3. Reading and writing can be performed by using the simplified backup func- tion. Refer to 2-4-3 Simplified Backup Function for details. 2-4-3 Simplified Backup Function The user program, Extended PC Setup, and IOM/DM data can be backed up from the CPU Unit to a Memory Card very simply without using a Programming...

  • Page 28: Setting Rack Numbers

    Section 2-6 I/O Control Unit and I/O Interface Unit Displays Setting Rack Numbers I/O words are allocated to Units mounted on the CPU, Expansion CPU, and CV- series Expansion I/O Racks by rack number, regardless of the order in which the Racks are connected.
  • Page 29 Section 2-6 I/O Control Unit and I/O Interface Unit Displays During online I/O Unit replacement, the slot number of the Unit that can be repla- ced is displayed. In the following example, the Unit in slot number 8 can be re- placed.
  • Page 30 Section 2-6 I/O Control Unit and I/O Interface Unit Displays Display Mode 4 In mode 4, the display shows the status of the duplex power supply. When an error has occurred, that information takes priority. Indicates mode 4. Indicates the status of the right Power Supply Unit. : Normal operation : Error occurred Abbreviation of “Power Supply”...
  • Page 31 SECTION 3 Memory Areas This section describes the way in which PC memory is broken into various areas used for different purposes. The contents of each area and addressing conventions, including the use of indirect addressing and addressing registers, are also described. Introduction .
  • Page 32 3-6-33 I/O Bus Error Flag and I/O Bus Error Slot/Rack Numbers ....3-6-34 Memory Error Flag ..........3-6-35 Duplex Bus Error Flag .

  • Page 33: Introduction

    Section 3-2 Data Area Structure Introduction Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally accessi- ble by the user for use in programming are classified as data areas.
  • Page 34 Section 3-2 Data Area Structure It is also possible to access any memory location through its hexadecimal inter- nal I/O memory address with indirect addressing. Refer to 3-9 DM and EM Areas, and 3-10 IR and DR Areas, for details on indirect addressing. Word Structure Memory areas are divided up into words, each of which consists of 16 bits num- bered 00 through 15 from right (least significant) to left (most significant).
  • Page 35 Unsigned binary Unsigned binary is the standard format used in OMRON PCs. Data in this manu- al are unsigned unless otherwise stated. Unsigned binary values are always positive and range from 0 ($0000) to 65,535 ($FFFF). Eight-digit values range from 0 ($0000 0000) to 4,294,967,295 ($FFFF FFFF).
  • Page 36 Section 3-2 Data Area Structure Signed Binary Signed binary data can have either a positive and negative value. The sign is indicated by the status of bit 15. If bit 15 is OFF, the number is positive and if bit 15 is ON, the number is negative.

  • Page 37: Cio (Core I/O) Area

    Section 3-3 CIO (Core I/O) Area CIO (Core I/O) Area CIO Area addresses run from words CIO 0000 through CIO 2555 and bits CIO 000000 through CIO 255515 and are divided into eight data areas. Five of these data areas are used to control I/O points and Special Units, and three data areas are used to manipulate and store data internally.
  • Page 38 Section 3-3 CIO (Core I/O) Area 3-3-1 I/O Area The I/O Area is used as data to control I/O points. Those words that are used to control I/O points are called I/O words. Bits in I/O words are called I/O bits. I/O Area bits that are not allocated as I/O bits are reset when power is interrupted or PC operation is stopped.
  • Page 39 Section 3-3 CIO (Core I/O) Area Word allocation begins with the leftmost Unit on the CPU Rack, and then contin- ues left to right on the CPU Expansion Rack or Expansion I/O Rack with the low- est rack number set on its I/O Interface Unit. The order in which the Expansion I/O Racks are connected is not relevant in word allocation, only the rack num- bers.
  • Page 40 Area and 3-3-8 SYSMAC BUS Area, for details. 5. 3G2A5-LK010-E I/O Link Units and C500-ETL01 Teaching Tool cannot be set to 16 point input/16 point output on a CVM1, CVM1D, or CV-series PC. 6. The I/O READ and I/O WRITE instructions (READ(190)/WRIT(191)) can be used for Units mounted to Slave Racks in SYSMAC BUS/2 Systems (but not in SYSMAC BUS Systems) under the following conditions.
  • Page 41 Section 3-3 CIO (Core I/O) Area Basic I/O Allocation I/O Word Allocation Example Starting point Rack #0 CPU Rack CPU Rack Expansion I/O Rack Expansion CPU Rack Rack #1 Empty slots or Units not Expansion I/O Rack Rack #1 requiring word allocation To next rack (no words allocated) Rack #3...
  • Page 42 Section 3-3 CIO (Core I/O) Area There are two ways, however, to change the I/O table registered in memory. One is to allocate words to a slot that is not currently being used. This method is de- scribed below in Word Reservations. The other way is to perform the I/O Table Registration operation again.
  • Page 43 Section 3-3 CIO (Core I/O) Area 3-3-3 SYSMAC BUS/2 Area I/O bits allocated in the SYSMAC BUS/2 Area correspond to I/O points on I/O Terminals (group-1 and group-2 Slaves), Units mounted to Slave Racks (group-3 Slaves), or other Units connected to SYSMAC BUS/2 Remote I/O Mas- ter Units (RM/2).

  • Page 44: Cpu Bus Unit Area

    Set. 3-3-6 CPU Bus Unit Area Two types of external bus are provided for CVM1, CVM1D, and CV-series PCs: the high-speed CPU bus (S Bus) and the I/O bus. Units that connect to the CPU bus on the CPU or Expansion CPU Rack are called CPU Bus Units and include...

  • Page 45: Tr (Temporary Relay) Area

    Section 3-5 CPU Bus Link Area SYSMAC BUS Area addresses range from CIO 2300 through CIO 2555. These 256 words are divided into 8 groups of 32 words each and are allocated to Mas- ters according their number setting. The following table shows the default ad- dress allocation.
  • Page 46 Section 3-5 CPU Bus Link Area PC Status Area The following table shows the specific functions of flags and control bits in the PC Status Area, G000. G000 Function bit(s) ON when the PC is in PROGRAM mode. ON when the PC is in DEBUG mode. ON when the PC is in MONITOR mode.
  • Page 47 Section 3-6 Auxiliary Area The 120 words of CPU Bus Link Area from G008 to G127 are used for outputs from the CPU to BASIC Units. The 128 words from G128 to G255 are used for outputs from the BASIC Units. These are divided into 16 groups of 8 words each and allocated to CPU Bus Units according their unit number settings as shown in the following tables.
  • Page 48 Section 3-6 Auxiliary Area Word(s) Bit(s) Function A008 00 to 06 Not used. (See note 1.) Stop Monitor Flag Execution Time Measured Flag Differentiate Monitor Completed Flag Stop Monitor Completed Flag Trace Trigger Monitor Flag Trace Completed Flag Trace Busy Flag Trace Start Bit Sampling Start Bit A009...
  • Page 49 Section 3-6 Auxiliary Area Word(s) Bit(s) Function A307 00 to 07 Programming Device Connected Flags for RT #0 to RT #7 of RM/2 #0 08 to 15 Programming Device Connected Flags for RT #0 to RT #7 of RM/2 #1 A308 00 to 07 Programming Device Connected Flags for RT #0 to RT...
  • Page 50 Section 3-6 Auxiliary Area Word(s) Bit(s) Function A399 00 to 07 Slot Undergoing Online I/O Replacement (2-digit BCD) 08 to 11 Rack Undergoing Online I/O Replacement (1-digit BCD) 12 to 13 Not used. Online I/O Replacement Status Retention Flag Online I/O Replacement In Progress Flag A400 00 to 15 Error Code...
  • Page 51 Section 3-6 Auxiliary Area Word(s) Bit(s) Function A422 00 to 15 CPU Bus Unit Error Unit Number A423 00 to 13 Not used. CPU Bus Unit Number Setting Error Flag CPU Bus Link Error Flag A424 00 to 03 SYSMAC BUS/2 Error Master Number 04 to 15 Not used.

  • Page 52: Iom Hold Bit

    Section 3-6 Auxiliary Area Word(s) Bit(s) Function A502 00 to 07 Port #0 to #7 Enabled Flags 08 to 15 Port #0 to #7 Execute Error Flags A503 to A510 00 to 15 Port #0 to #7 Completion Codes A511 00 to 04 Current EM Bank (0 to 7) 05 to 14...

  • Page 53: Sysmac Bus Error Check Bits

    Section 3-6 Auxiliary Area Do not turn these bits ON and OFF in the program; manipulate them from the SSS. 3-6-6 SYSMAC BUS Error Check Bits Bits A00500 through A00507 can be turned ON to read out the error codes (stored in words A470 through A477) for Masters numbered #0 through #7, re- spectively.

  • Page 54: Power Interruption Time

    Words A100 through A199 contain up to 20 records that show the nature, time, and date of errors that have occurred in the PC. The Error Log Area will store system-generated or FAL(006)/FALS(007)-generated error codes. Refer to Section 6 Troubleshooting in the CVM1D PCs Installation Guide for details on error codes.
  • Page 55 Section 3-6 Auxiliary Area The Error Log Area can be moved to the DM or EM Areas and its size can be increased to store up to 2,047 records with the PC Setup. Area Structure With the default PC Setup, error records occupy five words each stored between words A100 and A199.

  • Page 56: Macro Input/Output Areas

    Section 3-6 Auxiliary Area If there are words allocated for n errors and n errors occur, the next error will be written into the last position, n, the contents of previous error will be moved to record n–1, and so on until the contents of record 1 is moved off the end and lost, i.e., the area functions like a shift register that moves data in units of error re- cords (5 words).

  • Page 57: Cpu Bus Unit Service Interval

    Section 3-6 Auxiliary Area Word Bits 00 to 07 08 to 15 A307 Racks #0 to #7 on Master #0 Racks #0 to #7 on Master #1 A308 Racks #0 to #7 on Master #2 Racks #0 to #7 on Master #3 Programming Device Cycle Word A309 contains the cycle time in ms (in binary) required to service Program- Time (A309)

  • Page 58: Power Supply Unit Off/Error Flags

    Section 3-6 Auxiliary Area Duplex Program Mismatch Bit A39615 is turned ON when the programs do not match. Flag (A39614) 3-6-23 Power Supply Unit OFF/Error Flags CPU Rack PSU OFF Flags Bit A39700 is turned ON when the right Power Supply Unit in the CPU Rack is (A39700 and A39701) OFF or its start input terminals are open.

  • Page 59: Error Code

    When an error or alarm occurs, the error code is written to A400. If two errors occur simultaneously, the more serious error, with a higher error code, is re- corded. Refer to Section 6 Troubleshooting in the CVM1D PCs Installation Guide for details on error codes.

  • Page 60: Memory Error Flag

    Section 3-6 Auxiliary Area installed correctly. The rack/slot number of the Unit involved is written to word A404. Bits A40400 through A40407 contain the slot number, in BCD, of the I/O Unit where the error occurred. If the error did not occur with an I/O Unit, then these bits contain #0F.

  • Page 61: Sysmac Bus/2 Error Flag And Master/Unit Numbers

    Section 3-6 Auxiliary Area ber of the Master of the Remote I/O Subsystem involved. These numbers are assigned to Masters in the order that they are mounted to the CPU and Expan- sion Racks. If the error is in the Master, the value of bits 4 to 7 will be 8. If the error is in a Slave, bits 4 to 7 will contain the unit number of the Slave where the error occurred.

  • Page 62: I/O Verification Error Flag

    Section 3-6 Auxiliary Area 3-6-42 I/O Verification Error Flag Bit A40209 is turned ON when the Units mounted in the system disagree with the I/O table registered in the CPU. To ensure proper operation, PC operation should be stopped, Units checked, and the I/O table corrected whenever this flag goes ON.

  • Page 63: Maximum Cycle Time

    Section 3-6 Auxiliary Area 3-6-52 Maximum Cycle Time Words A462 and A463 contain the maximum cycle time that has occurred since operation was started. If the maximum cycle time is exceeded, however, the pre- vious maximum cycle time will remain in words A462 and A463. The time is re- corded in 8-digit BCD in tenths of milliseconds (0000000.0 ms to 9999999.9 ms), as shown in the following table.

  • Page 64: Step Flag

    Section 3-6 Auxiliary Area Negative Flag, N Bit A50008 is turned ON when the highest bit in the result of a calculation is ON. Overflow Flag, OF Bit A50009 is turned ON when the absolute value of the result is greater than the maximum value that can be expressed.

  • Page 65: Network Status Flags

    Section 3-8 Counter Area Caution The CPU may not be able to accurately read clock pulses if the cycle time is lon- ger than the pulse width. 3-6-59 Network Status Flags Bits A50200 through A50207 are turned ON to indicate that ports #0 through #7, respectively, are enabled for the SEND(192), RECV(193), and CMND(194).

  • Page 66: Dm And Em Areas

    Section 3-9 DM and EM Areas and its set value (SV) are defined using counter instructions. No prefix is re- quired when using a counter number to create a counter in a counter instruction. The same counter number can be defined using more than one of these instruc- tions as long as the instructions are not executed in the same cycle.
  • Page 67 Section 3-9 DM and EM Areas operand and D00010 as the second operand. When this instruction is executed, the content of CIO 0005 is compared with that of D00010. It is also possible, however, to use indirect DM and EM addresses as operands for instructions.

  • Page 68: Index And Data Registers (Ir And Dr)

    Section 3-10 Index and Data Registers (IR and DR) Indirect addressing can also be used in instructions that require bit operands for bits in the Core I/O Area ($0000 to $0FFF). These bits are designated by using the rightmost digits of the memory address as the leftmost three digits of the hex- adecimal address and adding the bit number as the rightmost digit.
  • Page 69 Section 3-10 Index and Data Registers (IR and DR) (030) Word Content Word Content D00000 +31,IR0 D00000 08FC CIO 1931 08FC 08FC moved to CIO 1931. Indirect address Register Content Indicates 078B 076C (CIO 1931) 078B If a Data Register is input before the “,” prefix, the content of the Data Register will be added to the content of the Index Register, and the result is the internal I/O memory address that is indirectly addressed.
  • Page 70 SECTION 4 Writing Programs This section explains the basic steps and concepts involved in writing a basic ladder diagram program. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution, along with a few other instructions of special interest in programming.

  • Page 71: Basic Procedure

    (timer/counter numbers are described in 5-13 Tim- er and Counter Instructions; jump numbers are described in this section.) 5. Draw the ladder diagram. (The CVM1D does not support SFC program- ming.) 6. Input the program into the CPU. Actual input is done from the SSS and is possible in either ladder diagram or mnemonic form.

  • Page 72: Basic Ladder Diagrams

    Section 4-3 Basic Ladder Diagrams Basic Ladder Diagrams A ladder diagram consists of two vertical lines running down the sides with lines branching in between them. The vertical lines are called bus bars; the branch- ing lines, instruction lines or rungs. Along the instruction lines are placed conditions that lead to other instructions next to the right bus bar.

  • Page 73: Basic Mnemonic Code

    Section 4-3 Basic Ladder Diagrams Execution Conditions In ladder diagram programming, the logical combination of ON and OFF condi- tions before an instruction determines the compound condition under which the instruction is executed. This condition, which is either ON or OFF, is called the execution condition for the instruction.

  • Page 74: Ladder Instructions

    Section 4-3 Basic Ladder Diagrams used. All other instructions are written with the instruction on the first line fol- lowed by the operands one to a line. An example of mnemonic code is shown below. The instructions used in it are described later in the manual. When input- ting programs in mnemonic form from the SSS, most operands are separated only by spaces.
  • Page 75 Section 4-3 Basic Ladder Diagrams When this is the only condition on the instruction line, the execution condition for the instruction at the right is ON when the execution condition is ON. For the LOAD instruction (i.e., a normally open condition), an ON execution condition would be produced when CIO 000000 was ON;...

  • Page 76: Output And Output Not

    Section 4-3 Basic Ladder Diagrams Combining AND and OR When AND and OR instructions are combined in more complicated diagrams, Instructions they can sometimes be considered individually, with each instruction performing a logic operation on the current execution condition and the status of the oper- and bit.

  • Page 77: The End Instruction

    Section 4-4 Mnemonic Code 4-3-5 The END Instruction The last instruction required to complete any program is the END instruction. When the CPU scans a program, it executes all instructions up to the first END instruction before returning to the beginning of the program and beginning execution again.
  • Page 78 Section 4-4 Mnemonic Code The above ladder diagram cannot be converted to mnemonic code using AND and OR instructions alone. If an AND between CIO 000002 and the results of an OR between CIO 000000 and CIO 000001 is attempted, the OR NOT between CIO 000002 and CIO 000003 is lost and the OR NOT ends up being an OR NOT between just CIO 000003 and the result of an AND between CIO 000002 and the first OR.
  • Page 79 Section 4-4 Mnemonic Code all logic block instructions together, can be used only if eight or fewer blocks are being combined, i.e., if seven or fewer logic block instructions are required. The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series.
  • Page 80 Section 4-4 Mnemonic Code The first of each pair of conditions is converted to LOAD with the assigned bit operand and then ANDed with the other condition. The first two blocks can be coded first, followed by OR LOAD, the last block, and another OR LOAD, or the three blocks can be coded first followed by two OR LOADs.
  • Page 81 Section 4-4 Mnemonic Code Complicated Diagrams When determining what logic block instructions will be required to code a dia- gram, it is sometimes necessary to break the diagram into large blocks and then continue breaking the large blocks down until logic blocks that can be coded without logic block instructions have been formed.
  • Page 82 Section 4-4 Mnemonic Code The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mne- monic code. 0000 0000 0002 Address Instruction Operands 00000...
  • Page 83 Section 4-4 Mnemonic Code Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space. 0000 0000 0000 0000 0000 0002 Address Instruction Operands 00000 000006 0000 00001 000007 00002 000005 00003 000003 0000 0000...

  • Page 84: Coding Multiple Right-Hand Instructions

    Section 4-5 Branching Instruction Lines 4-4-2 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same execu- tion condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with CIO 000400.

  • Page 85: Tr Bits

    Section 4-5 Branching Instruction Lines 4-5-1 TR Bits The TR area provides eight bits, TR0 through TR7, that can be used to tempo- rarily preserve execution conditions. If a TR bit is placed at a branching point, the current execution condition will be stored at the designated TR bit. When return- ing to the branching point, the TR bit restores the execution status that was saved when the branching point was first reached in program execution.
  • Page 86 Section 4-5 Branching Instruction Lines In this example, TR0 and TR1 are used to store the execution conditions at the branching points. After executing instruction 1, the execution condition stored in TR1 is loaded for an AND with the status CIO 000003. The execution condition stored in TR0 is loaded twice, the first time for an AND with the status of CIO 000004 and the second time for an AND with the inverse of the status of CIO 000005.

  • Page 87: Interlocks

    Section 4-5 Branching Instruction Lines 4-5-2 Interlocks The problem of storing execution conditions at branching points can also be handled by using the INTERLOCK (IL(002)) and INTERLOCK CLEAR (ILC(003)) instructions to eliminate the branching point completely while allow- ing a specific execution condition to control a group of instructions. The INTER- LOCK and INTERLOCK CLEAR instructions are always used together.

  • Page 88: Jumps

    Section 4-6 Jumps As shown below, multiple INTERLOCK instructions can be used in one instruc- tion block; each is effective through the next INTERLOCK CLEAR instruction. 0000 Address Instruction Operands (002) 00000 000000 0000 00001 IL(002) Instruction 1 00002 000001 0000 00003 Instruction 1...
  • Page 89 JMP 0000 before the next JME 0000 in the program. CVM1D CPUs also support the CJP(221) and CJPN(222) jump instructions that can also be used to create jumps in programs. Refer to Section 5 Instruction Set...

  • Page 90: Controlling Bit Status

    OFF (CIO 000200 will be kept OFF until then), and will be turned OFF the next time DIFD(014) 000200 is executed. CVM1D CPUs also provide UP(018) and DOWN(019) that can be used to differ- entiate changes in the execution condition to control execution. Refer to Section 5 Instruction Set for details.

  • Page 91: Keep

    Section 4-7 Controlling Bit Status 4-7-3 KEEP The KEEP instruction is used to maintain the status of the operand bit based on two execution conditions. To do this, the KEEP instruction is connected to two instruction lines. When the execution condition at the end of the first instruction line is ON, the operand bit of the KEEP instruction is turned ON.

  • Page 92: Intermediate Instructions

    Section 4-9 Work Bits (Internal Relays) Intermediate Instructions There are some instructions that can appear on instructions lines with conditions to help determine the execution conditions for other instructions. These instruc- tions are called intermediate instructions. Intermediate instructions cannot be placed next to the right bus bar, only between conditions or between a condition and a right-hand instruction.
  • Page 93 Section 4-9 Work Bits (Internal Relays) Reducing Complex Work bits can be used to simplify programming when a certain combination of Conditions conditions is repeatedly used in combination with other conditions. In the follow- ing example, CIO 000000, CIO 000001, CIO 000002, and CIO 000003 are com- bined in a logic block that stores the resulting execution condition as the status of CIO 024600.

  • Page 94: Programming Precautions

    Section 4-10 Programming Precautions 4-10 Programming Precautions The number of conditions that can be used in series or parallel is unlimited as long as the memory capacity of the PC is not exceeded. Therefore, use as many conditions as required to draw clear diagrams. Although very complicated dia- grams can be drawn with instruction lines, there must not be any conditions on lines running vertically between two other instruction lines.

  • Page 95: Program Execution

    Section 4-12 Data Formats When drawing ladder diagrams, it is important to keep in mind the number of instructions that will be required to input it. In diagram A, below, an OR LOAD instruction will be required to combine the top and bottom instruction lines. This can be avoided by redrawing as shown in diagram B so that no AND LOAD or OR LOAD instructions are required.

  • Page 96: Signed Binary Data

    Section 4-12 Data Formats following example shows status 0000 “0011110000001110.” This would be represented as “3C0E” in hexadecimal. ON/OFF Digit Conversion to Decimal With unsigned binary data, the digits expressed in hexadecimal can be con- verted to decimal by multiplying the value of each digit by its respective factor. For example, the hexadecimal value “3C0E”...
  • Page 97 Section 4-12 Data Formats When the sign bit is ON, on the other hand, the number will be negative, and the method for converting to decimal will be different. Because the value is ex- pressed in 2’s complement, it must first be converted to a negative number and then the value of each digit can be multiplied by its respective factor.
  • Page 98 Section 4-12 Data Formats Signed Binary Data The following instructions carry out calculations on signed binary data. Calculations Operation Mnemonic Code Name Addition SIGNED BINARY ADD WITHOUT CARRY DOUBLE SIGNED BINARY ADD WITHOUT CARRY SIGNED BINARY ADD WITH CARRY DOUBLE SIGNED BINARY ADD WITH CARRY Subtraction –...

  • Page 99: Bcd Data

    Section 5 Instruction Set. 4-12-5 Floating-point Data Floating-point data is stored as 2-word (32-bit) data in a format defined in IEEE754. The CVM1D CPUs provide a number of floating-point operation instructions, including math instructions, logarithms, exponents. All of these handle floating-point data.
  • Page 100 Instruction Set This section explains each instruction in the CVM1D PC instruction set and provides the ladder diagram symbols, data areas, and flags used with each. The instructions provided by the CVM1D PC are described in following subsections by instruction group.
  • Page 101 5-14-9 DOUBLE SHIFT N-BITS LEFT: NSLL(058) ......5-14-10 DOUBLE SHIFT N-BITS RIGHT: NSRL(059) ......5-14-11 ARITHMETIC SHIFT LEFT: ASL(060) .
  • Page 102 5-17-9 DATA ENCODER: DMPX(111) ........5-17-10 7-SEGMENT DECODER: SDEC(112) .
  • Page 103 5-21-14 SINE TO ANGLE: ASIN(463) ........5-21-15 COSINE TO ANGLE: ACOS(464) .
  • Page 104 5-28-1 LOAD FLAGS: CCL(172) ......... . 5-28-2 SAVE FLAGS: CCS(173) .

  • Page 105: Notation

    Section 5-3 Data Areas, Definers, and Flags Notation In the remainder of this manual, instructions will be referred to by their mnemon- ics. For example, the OUTPUT instruction will be called OUT; the AND LOAD instruction, AND LD. If you’re not sure of the instruction a mnemonic is for, refer to Appendix B Programming Instructions.
  • Page 106 Section 5-3 Data Areas, Definers, and Flags Basic Ladder Symbol The ladder symbol shows how the instruction will appear in a program. The func- tion code (here, 143) is provided above the mnemonic (SEC) and the operands are provided to the right (here, S and R). The ladder symbol is the same for any of the variations of the instruction except that the mnemonic changes.
  • Page 107 Section 5-3 Data Areas, Definers, and Flags Flags The Flags subsection lists flags that are affected by execution of an instruction. These flags include the following Auxiliary Area flags. Abbreviation Name Instruction Execution Error Flag A50003 Carry Flag A50004 Greater Than Flag A50005 Equals Flag A50006...

  • Page 108: Differentiated And Immediate Refresh Instructions

    Section 5-4 Differentiated and Immediate Refresh Instructions When indirect DM data is designated as binary, the content of the *D or *E ad- Binary Indirect Addressing dress specifies the PC memory address, and thus can have any value between $0000 and $FFFF, as long as the instruction can be executed with the specified PC memory address.
  • Page 109 JUMP and JUMP END – JMP(004) and JME(005), and 5-30 Subroutines for de- tails. CVM1D PCs also provide differentiation instructions: DIFU(013) and DIFD(014). These instruction operate as the differentiated variations of the OUTPUT instruction: DIFU(013) turns ON a bit for one cycle when the execution condition has changed from OFF to ON and DIFD(014) turns ON a bit for one cycle when the execution condition has changed from ON to OFF.

  • Page 110: Coding Right-Hand Instructions

    Section 5-5 Coding Right-hand Instructions The I/O response time is reduced with an immediate refresh instruction because status is read from the input bit or written to the output bit without waiting for the next I/O refresh period. Refer to 6-5 I/O Response Time for details on the effects of immediate refresh instructions on I/O response time.
  • Page 111 Section 5-5 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Operands 00000 000000 00001 000001 0000 0000 (013) 00002 000002 DIFU 022500 00003 DIFU(013) 022500 0000 00004 000100 00005 AND NOT 000200 0001 0002...

  • Page 112: Ladder Diagram Instructions

    Section 5-6 Ladder Diagram Instructions Ladder Diagram Instructions Ladder Diagram Instructions include Ladder Instructions and Logic Block Instructions. Ladder Instructions correspond to the conditions on the ladder diagram. Logic Block Instructions are used to relate more complex parts of the diagram that cannot be programmed with Ladder Instructions alone. 5-6-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT LOAD: LD Ladder Symbols...
  • Page 113 Section 5-6 Ladder Diagram Instructions OR: OR Ladder Symbols Operand Data Area B: Bit CIO, G, A, T, C Mnemonics ! j OR ! i OR j OR i OR ! OR OR NOT: OR NOT Ladder Symbols Operand Data Area B: Bit CIO, G, A, T, C Mnemonics...

  • Page 114: Condition On/Off: Up(018) And Down

    Section 5-6 Ladder Diagram Instructions 5-6-2 CONDITION ON/OFF: UP(018) and DOWN(019) Ladder Symbols (018) (019) DOWN Description UP(018) turns ON the execution condition for one cycle at the rising edge (OFF to ON) of the execution condition and then turns OFF the execution condition until the next time a rising edge is detected.

  • Page 115: Bit Test: Tst(350) And Tstn

    Section 5-6 Ladder Diagram Instructions 5-6-3 BIT TEST: TST(350) and TSTN(351) Ladder Symbol Operand Data Areas (350) S: Source word CIO, G, A, DM, DR, IR TST S N N: Bit number CIO, G, A, T, C, #, DM, DR, IR (351) TSTN S N Description...

  • Page 116: Not: Not(010)

    Section 5-6 Ladder Diagram Instructions 5-6-4 NOT: NOT(010) Ladder Symbol (010) Description NOT(010) reverses the execution condition. NOT(010) is an intermediate instruction that inverts the execution condition that precedes it. As an intermediate instruction, it cannot be placed at the end of an instruction line, only between conditions or between a condition and a right-hand instruction.

  • Page 117: Bit Control Instructions

    Section 5-7 Bit Control Instructions Bit Control Instructions The instructions in this section are used to control bit status. These instructions are used to turn bits ON and OFF in different ways. 5-7-1 OUTPUT and OUTPUT NOT: OUT and OUT NOT OUTPUT: OUT Ladder Symbols Operand Data Area...

  • Page 118: Differentiate Up/Down: Difu(013) And Difd

    Section 5-7 Bit Control Instructions 5-7-2 DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014) DIFFERENTIATE UP: DIFU(013) Ladder Symbol Operand Data Area (013) B: Bit CIO, G, A DIFU Variations !DIFU(013) DIFFERENTIATE DOWN: DIFD(014) Ladder Symbol Operand Data Area (014) B: Bit CIO, G, A DIFD Variations !DIFD(014)
  • Page 119 Section 5-7 Bit Control Instructions Example 1: Use when In diagram A, below, whenever MOVQ(037) is executed with an ON execution There’s No Differentiated condition it will move the contents of CIO 1200 to A001. If the execution condition Instruction remains ON, the content of A001 will be changed each cycle that the content of CIO 1200 changes.

  • Page 120: Set And Reset: Set(016) And Rset

    Section 5-7 Bit Control Instructions 5-7-3 SET and RESET: SET(016) and RSET(017) SET: SET(016) Ladder Symbol Operand Data Area (016) B: Bit CIO, G, A Variations jSET(016) iSET(016) !SET(016) !jSET(016) !iSET(016) RESET: RSET(017) Ladder Symbol Operand Data Area (017) B: Bit CIO, G, A RSET Variations...

  • Page 121: Multiple Bit Set/Reset: Seta(047)/Rsta

    Section 5-7 Bit Control Instructions Precautions The status of operand bits for SET(016) and RSET (017) programmed between IL(002) and ILC(003) or JMP(004) and JME(005) will not change when the inter- lock or jump condition is met (i.e., when IL(002) or JMP(004) is executed with an OFF execution condition).
  • Page 122 Section 5-7 Bit Control Instructions Precautions must be between 0000 and 0015 and must be BCD. N must be BCD. Note: Refer to page 101 for general precautions on operand data areas. Flags ER (A50003): is not 0000 to 0015 BCD. is not BCD.

  • Page 123: Keep: Keep(011)

    Section 5-7 Bit Control Instructions CIO 0005 Unchanged CIO 0006 Unchanged CIO 0007 CIO 0010 Unchanged CIO 0011 Unchanged CIO 0012 5-7-5 KEEP: KEEP(011) Ladder Symbol Operand Data Area (011) B: Bit CIO, G, A KEEP Variations !KEEP(011) Description KEEP(011) is used to maintain the status of the designated bit based on two execution conditions.
  • Page 124 Section 5-7 Bit Control Instructions KEEP(011) operates like the self-maintaining bit described in 4-7-4 Self-main- taining Bits (Seal). The following two diagrams would function identically, though the one using KEEP(011) requires one less instruction to program and would maintain status even in an interlocked program section. Address Instruction Operands 0000 0000...

  • Page 125: Interlock And Interlock Clear: Il(002) And Ilc(003

    Section 5-8 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) Example If a holding bit (default range: CIO 1200 to CIO 1499) is used, bit status will be retained even during a power interruption. KEEP(011) can thus be used to pro- gram bits that will maintain status after restarting the PC following a power inter- ruption.
  • Page 126 Section 5-8 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) If the execution condition for IL(002) is OFF, the interlocked section between IL(002) and ILC(003) will be treated as shown in the following table: Instruction Treatment OUT and OUT NOT Designated bit turned OFF. TIM, TIMH(015), and TIML(121) Reset.

  • Page 127: Jump And Jump End: Jmp(004) And Jme(005

    Section 5-9 JUMP and JUMP END: JMP(004) and JME(005) Example The following diagram shows IL(002) being used twice with one ILC(003). 0000 (002) Address Instruction Operands 00000 000000 0000 00001 IL(002) 0511 #0015 1.5 s 00002 000001 0000 00003 T00511 (002) #0015 0000...
  • Page 128 Section 5-9 JUMP and JUMP END: JMP(004) and JME(005) Only one JME(005) instruction per jump number should be used in a program. If two or more JME(005) instructions with the same jump number are used in a program, program execution will skip to the JME(005) instruction at the lowest program address, even if it precedes the JMP(004) instruction.
  • Page 129 JUMP and JUMP END: JMP(004) and JME(005) Timer Operation in Jumps The operation of timers in CVM1D PCs is the same as in C-series, CVM1, and CV-series PCs, although timer PVs are refreshed differently in jumped program sections. The following table describes the operation of timers in a jumped pro- gram section, i.e., when the execution condition for the JMP(004) controlling the...

  • Page 130: Conditional Jump: Cjp(221)/Cjpn

    Section 5-10 CONDITIONAL JUMP: CJP(221)/CJPN(222) When the JMP(004) instruction’s execution condition is turned OFF after tim- ing has been started by turning ON the timer’s execution condition (b), timing will continue but the timer PV will not be refreshed. Be sure to consider the effects of the JMP(004)/JME(005) instructions on timer PVs when using the timer PVs as data in the program.

  • Page 131: End: End(001)

    Section 5-12 NO OPERATION – NOP(00) If there are two or more JME(005) instructions in a program for the same jump number, the one at the lower address is valid and the ones at higher addresses are ignored. 0000 (221) When the execution condition (CIO 000000) is ON, the program CJP #0100 up to the JME(005) instruction with jump number 0100 is ignored.

  • Page 132: Timer And Counter Instructions

    Section 5-13 Timer and Counter Instructions 5-13 Timer and Counter Instructions Timers The timer instructions in this section are used to create timers. Most timers re- quire a timer number and a set value (SV). Timer numbers run from T0000 through T1023, and are used to access timer PVs and Completion Flags in memory areas set aside specifically for this purpose.
  • Page 133 Section 5-13 Timer and Counter Instructions Indirect Addressing 10.Timer and counter numbers for TIM, TIMH(015), TTIM(120), CNT, CNTR(012), TIMW<013>, CNTW<014>, and TMHW<015> can be indirectly addressed using the Index Registers by moving the PC memory address of the PV of the timer or counter number to the Index Register. PVs for timers T0000 through T1023 are contained in PC memory addresses $1000 through $13FF, and PVs for counters C0000 through C1023 are contained in PC memory ad- dresses $1800 through $1BFF.

  • Page 134: Timer: Tim

    Section 5-13 Timer and Counter Instructions The first MOV(030) instruction moves the PC memory address of the PV for tim- er T0000 ($1000) to IR0. The first MOVR(036) instruction moves the PC memory address of the Completion Flag for timer T0000 to IR1, and the second one moves the starting address into IR2.
  • Page 135 TIM and the Completion Flag assigned to it. Execution condition Completion Flag Differences in CVM1D and Operation of the TIM instruction is the same in CVM1D and C/CVM1/CV-series PCs except for the timer precision and PV refreshing in jumped program sec- C/CVM1/CV-series PCs tions.
  • Page 136 Section 5-13 Timer and Counter Instructions Example 1: The following example shows two timers, one set with a constant and one set via Basic Application input word 0005. Here, 000200 will be turned ON after 000000 goes ON and stays ON for at least 15 seconds. When 000000 goes OFF, the timer will be reset and 000200 will be turned OFF.
  • Page 137 Section 5-13 Timer and Counter Instructions 1In the following example, 000500 would be turned ON 5.0 seconds after 000000 goes ON and then turned OFF 3.0 seconds after 000000 goes OFF. It is necessary to use both 000500 and 000000 to determine the execution condition for T0002;...

  • Page 138: High-Speed Timer: Timh(015)

    0.01 second. Refer to 5-13-1 TIMER: TIM for operational details and ex- amples. Differences in CVM1D and Operation of TIMH(015) is the same in CVM1D and C/CVM1/CV-series PCs ex- cept for the timer precision and PV refreshing in jumped program sections. C/CVM1/CV-series PCs 1, 2, 3...
  • Page 139 Section 5-13 Timer and Counter Instructions 2. Operation of the TIMH(015) Instruction between JMP(004) and JME(005) • The timer PV is refreshed every cycle during program execution. • The timer operates normally while the execution condition of JMP(004) is • The timer PV is not refreshed while the timer is jumped (while the execu- tion condition of JMP(004) is OFF.) If the timer is jumped after it has started timing, the timer count will contin- ue decrementing but the PV will not be refreshed.

  • Page 140: Accumulative Timer: Ttim(120)

    Reset input (R) Completion Flag (T0128) Present value: 0100 0000 Differences in CVM1D and Operation of TTIM(120) is the same in CVM1D and C/CVM1/CV-series PCs ex- cept for the timer precision and PV refreshing in jumped program sections. C/CVM1/CV-series PCs...
  • Page 141 Section 5-13 Timer and Counter Instructions 1, 2, 3... 1. Timer Precision TTIM(120) instruction errors can be one cycle time or more (up to two cycle times). The error range is ± (10 ms + cycle time). 2. Operation of the TTIM(120) Instruction between JMP(004) and JME(005) •...

  • Page 142: Long Timer: Timl(121)

    S and S+1. Bits 01 through 15 of D cannot be used. Differences in CVM1D and Operation of TIML(121) is the same in CVM1D and C/CVM1/CV-series PCs ex- cept for the timer precision and PV refreshing in jumped program sections. C/CVM1/CV-series PCs 1, 2, 3...

  • Page 143: Multi-Output Timer: Mtim(122)

    Section 5-13 Timer and Counter Instructions Power interruptions will reset timers unless the IOM Hold Bit and PC Setup are set to retain timer PVs during power interruptions. If a timer that is not reset un- der these conditions is desired, Auxiliary Area clock pulse bits can be counted to produce accumulative timers using CNT.
  • Page 144 (Bit 0n contains the Flag for the SV in S+n.) Differences in CVM1D and Operation of MTIM(122) is the same in CVM1D and C/CVM1/CV-series PCs ex- cept for the timer precision and PV refreshing in jumped program sections. C/CVM1/CV-series PCs 1, 2, 3...

  • Page 145: Counter: Cnt

    Section 5-13 Timer and Counter Instructions Note: Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): Example Timing will start in the following example when CIO 000000 is ON and CIO 000508 changes from OFF to ON.
  • Page 146 Section 5-13 Timer and Counter Instructions The counter will not restarted after it has counted down to zero until it is reset by turning ON R or executing CNR(236). Changes in execution conditions, the Completion Flag, and the PV are illus- trated below.
  • Page 147 Section 5-13 Timer and Counter Instructions The above CNT can be modified to restart from SV each time power is turned ON to the PC. This is done by using the First Cycle Flag in the Auxiliary Area (A50015) to reset CNT as shown below. 0000 0000 Address Instruction...
  • Page 148 Section 5-13 Timer and Counter Instructions In the following example, C0002 counts the number of times T0001 reaches zero from its SV. The Completion Flag for T0001 is used to reset T0001 so that it runs continuously and C0002 counts the number of times the Completion Flag for T0001 goes ON (C0002 would be executed once each time between when the Completion Flag for T0001 goes ON and T0001 is reset by its Completion Flag).

  • Page 149: Reversible Counter: Cntr(012)

    Section 5-13 Timer and Counter Instructions 5-13-7 REVERSIBLE COUNTER: CNTR(012) Ladder Symbol Operand Data Areas (012) N: Counter number # CNTR S: Set value CIO, G, A, T, C, #, DM, DR, IR *Refer to page 128 for details on indirectly addressing counters. Description The CNTR(012) is a reversible, up/down circular counter, i.e., it is used to count between zero and SV according to changes in two execution conditions, those...

  • Page 150: Reset Timer/Counter: Cnr(236)

    Section 5-13 Timer and Counter Instructions Counter numbers range from C0000 through C1023. Each counter number can be used to define only one counter instruction unless the counters are never ac- tive simultaneously. The CNT and CNTR(012) counters use counter numbers. Note: Refer to page 101 for general precautions on operand data areas.
  • Page 151 Section 5-13 Timer and Counter Instructions Precautions and D must be in the same data area, and D must be less than or equal to . If D , only D will be reset. Note: Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD.

  • Page 152: Shift Instructions

    Section 5-14 Shift Instructions 5-14 Shift Instructions All of the Shift Instructions are used to shift data within or between words, but in differing amounts and directions. 5-14-1 SHIFT REGISTER: SFT(050) Ladder Symbol Operand Data Areas (050) St: Starting word CIO, G, A E: End word CIO, G, A...
  • Page 153 Section 5-14 Shift Instructions Example 1: The following example uses the 1-second clock pulse bit (A50102) so that the Basic Application execution condition produced by CIO 000005 is shifted into a 3-word register between CIO 0128 and CIO 0130 every second. Address Instruction Operands 0000...
  • Page 154 Section 5-14 Shift Instructions The program is set up so that a rotary encoder (000000) controls execution of SFT(050) through a DIFU(013), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor. Another sensor (000002) is used to detect faulty products in the chute so that the pusher output and bit 120003 of the shift register can be reset as required.

  • Page 155: Reversible Shift Register: Sftr(051)

    Section 5-14 Shift Instructions 5-14-2 REVERSIBLE SHIFT REGISTER: SFTR(051) Ladder Symbol Operand Data Areas (051) C: Control word CIO, G, A, DM, DR, IR SFTR St: Starting word CIO, G, A, DM Variations E: End word CIO, G, A, DM j SFTR(051) Description SFTR(051) is used to create a single- or multiple-word shift register that can shift...

  • Page 156: Asynchronous Shift Register: Asft(052)

    Section 5-14 Shift Instructions Example In the following example, CIO bits 000005, 000006, 000007, and 000008 are used to control the bits of C used in j SFTR(051). The shift register is between words 0020 and 0021, and it is controlled through bit 000009. Address Instruction Operands...
  • Page 157 Section 5-14 Shift Instructions Control Word Bits 00 through 12 of C are not used. Bit 13 is the shift direction: turn bit 13 OFF to shift the non-zero data toward E (toward higher addressed words) and ON to shift toward St (toward lower addressed words). Bit 14 is the Shift Enable Bit: turn bit 14 OFF to enable shift register operation according to bit 13, and ON to disable the register.

  • Page 158: Word Shift: Wsft(053)

    Section 5-14 Shift Instructions 5-14-4 WORD SHIFT: WSFT(053) Ladder Symbol Operand Data Areas (053) S: Source word CIO, G, A, T, C, #, DM, DR, IR WSFT St: Starting word CIO, G, A, DM Variations E: End word CIO, G, A, DM j WSFT(053) Description When the execution condition is OFF, WSFT(053) is not executed.

  • Page 159: Shift N-Bit Data Left: Nsfl(054)

    Section 5-14 Shift Instructions 5-14-5 SHIFT N-BIT DATA LEFT: NSFL(054) Ladder Symbol Operand Data Areas D: Beginning word for shift CIO, G, A NSFL D C N C: Beginning bit CIO, G, A, T, C, #, DM, DR, IR N: Shift data length CIO, G, A, T, C, #, DM, DR, IR Variations ↑NSFL(054)

  • Page 160: Shift N-Bit Data Right: Nsfr(055)

    Section 5-14 Shift Instructions D+1: Wd 0002 D: Wd 0001 N: 18 bits 0 0 0 1 1 After one execution 0 0 0 1 1 5-14-6 SHIFT N-BIT DATA RIGHT: NSFR(055) Ladder Symbol Operand Data Areas NSFR D C N D: Beginning word for shift CIO, G, A C: Beginning bit CIO, G, A, T, C, #, DM, DR, IR...

  • Page 161: Shift N-Bits Left: Nasl(056)

    Section 5-14 Shift Instructions Example When CIO 000000 is ON in the following example, the18 bits of data beginning from bit 03 of CIO 0001 are shifted to the right, one at a time. A “0” is entered for the beginning bit (CIO 000204) of the shift. The status of bit CIO 000103 is shifted to CY.

  • Page 162: Shift N-Bits Right: Nasr(057)

    Section 5-14 Shift Instructions After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the rightmost bit of the specified word) will be set to “0” or to the status of the LSB, depending on the control word setting.

  • Page 163: Double Shift N-Bits Left: Nsll(058)

    Section 5-14 Shift Instructions After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the leftmost bit of the specified word) will be set to “0” or to the status of the MSB, depending on the control word setting.
  • Page 164 Section 5-14 Shift Instructions After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the rightmost bit of the specified word) will be set to “0” or to the status of the LSB, depending on the control word setting.

  • Page 165: Double Shift N-Bits Right: Nsrl(059)

    Section 5-14 Shift Instructions 5-14-10 DOUBLE SHIFT N-BITS RIGHT: NSRL(059) Operand Data Areas Ladder Symbol NSRL D C D: Shift word address CIO, G, A, DM, C: Control word CIO, G, A, T, C, #, DM, Variations ↑NSRL(059) Description When the execution condition is OFF, NSRL(059) is not executed. When the ex- ecution condition is ON, NSRL(059) shifts the status of the 32 bits in the speci- fied words to the right the specified number of bits.

  • Page 166: Arithmetic Shift Left: Asl(060)

    Section 5-14 Shift Instructions Lost 0 entered. 5-14-11 ARITHMETIC SHIFT LEFT: ASL(060) Ladder Symbol Operand Data Area (060) Wd: Word CIO, G, A, DM, Variations j ASL(060) Description When the execution condition is OFF, ASL(060) is not executed. When the ex- ecution condition is ON, ASL(060) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.

  • Page 167: Arithmetic Shift Right: Asr(061)

    Section 5-14 Shift Instructions 5-14-12 ARITHMETIC SHIFT RIGHT: ASR(061) Ladder Symbol Operand Data Area (061) Wd: Word CIO, G, A, DM, DR, IR Variations j ASR(061) Description When the execution condition is OFF, ASR(061) is not executed. When the ex- ecution condition is ON, ASR(061) shifts a 0 into bit 15 of Wd, shifts the bits of Wd one bit to the right, and shifts the status of bit 00 into CY.

  • Page 168: Rotate Left: Rol(062)

    Section 5-14 Shift Instructions 5-14-13 ROTATE LEFT: ROL(062) Ladder Symbol Operand Data Area (062) Wd: Word CIO, G, A, DM, DR, IR Variations j ROL(062) Description When the execution condition is OFF, ROL(062) is not executed. When the ex- ecution condition is ON, ROL(062) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY.

  • Page 169: Rotate Right: Ror(063)

    Section 5-14 Shift Instructions 5-14-14 ROTATE RIGHT: ROR(063) Ladder Symbol Operand Data Area (063) Wd: Word CIO, G, A, DM, DR, IR Variations j ROR(063) Description When the execution condition is OFF, ROR(063) is not executed. When the ex- ecution condition is ON, ROR(063) shifts all Wd bits one bit to the right, shifting CY into bit 15 of Wd and shifting bit 00 of Wd into CY.

  • Page 170: Double Shift Left: Asll(064)

    Section 5-14 Shift Instructions 5-14-15 DOUBLE SHIFT LEFT: ASLL(064) Ladder Symbol Operand Data Area (064) Wd: Word CIO, G, A, DM ASLL Wd Variations j ASLL(064) Description When the execution condition is OFF, ASLL(064) is not executed. When the ex- ecution condition is ON, ASLL(064) shifts a 0 into bit 00 of Wd, all bits previously in Wd and Wd+1 are shifted to the left, and bit 15 of Wd+1 is shifted into CY.

  • Page 171: Double Shift Right: Asrl(065)

    Section 5-14 Shift Instructions 5-14-16 DOUBLE SHIFT RIGHT: ASRL(065) Ladder Symbol Operand Data Area (065) Wd: Word CIO, G, A, DM ASRL Wd Variations j ASRL(065) Description When the execution condition is OFF, ASRL(065) is not executed. When the ex- ecution condition is ON, ASRL(065) shifts a 0 into bit 15 of Wd+1, all bits pre- viously in Wd and Wd+1 are shifted to the right, and bit 00 of Wd is shifted into Wd+1...

  • Page 172: Double Rotate Left: Roll(066)

    Section 5-14 Shift Instructions 5-14-17 DOUBLE ROTATE LEFT: ROLL(066) Ladder Symbol Operand Data Area (066) Wd: Word CIO, G, A, DM ROLL Wd Variations j ROLL(066) Description When the execution condition is OFF, ROLL(066) is not executed. When the ex- ecution condition is ON, ROLL(066) shifts CY into bit 00 of Wd, all bits previously in Wd and Wd+1 are shifted to the left, and bit 15 of Wd+1 is shifted into CY.

  • Page 173: Rotate Left Without Carry: Rlnc(260)

    Section 5-14 Shift Instructions 5-14-18 ROTATE LEFT WITHOUT CARRY: RLNC(260) Ladder Symbol Operand Data Area (260) Wd: Word CIO, G, A, DM, DR, IR RLNC Wd Variations ↑RNLC(260) Description When the execution condition is OFF, RLNC(260) is not executed. When the ex- ecution condition is ON, RLNC(260) shifts all Wd bits one bit to the left, shifting the status of bit 15 of Wd into both bit 00 and CY.

  • Page 174: Double Rotate Left Without Carry: Rlnl(262)

    Section 5-14 Shift Instructions 5-14-19 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(262) Ladder Symbol Operand Data Area (262) Wd: Word CIO, G, A, DM RLNL Wd Variations ↑RLNL(262) Description When the execution condition is OFF, RLNL(262) is not executed. When the ex- ecution condition is ON, RLNL(262) shifts all bits previously in Wd and Wd+1 to the left, and bit 15 of Wd+1 is shifted into both bit 00 of Wd and into CY.

  • Page 175: Double Rotate Right: Rorl(067)

    Section 5-14 Shift Instructions 5-14-20 DOUBLE ROTATE RIGHT: RORL(067) Ladder Symbol Operand Data Area (067) Wd: Word CIO, G, A, DM RORL Wd Variations j RORL(067) When the execution condition is OFF, RORL(067) is not executed. When the ex- Description ecution condition is ON, RORL(067) shifts CY into bit 15 of Wd+1, all bits pre- viously in Wd and Wd+1 are shifted to the right, and bit 00 of Wd is shifted into Wd+1...

  • Page 176: Rotate Right Without Carry: Rrnc(261)

    Section 5-14 Shift Instructions 5-14-21 ROTATE RIGHT WITHOUT CARRY: RRNC(261) Ladder Symbol Operand Data Area (261) Wd: Word CIO, G, A, DM, DR, IR RRNC Wd Variations ↑RRNC(261) Description When the execution condition is OFF, RRNC(261) is not executed. When the execution condition is ON, RRNC(261) shifts all Wd bits one bit to the right, shift- ing the status of bit 00 into both bit 15 of Wd and into CY.

  • Page 177: Double Rotate Right W/O Carry: Rrnl(263)

    Section 5-14 Shift Instructions 5-14-22 DOUBLE ROTATE RIGHT W/O CARRY: RRNL(263) Ladder Symbol Operand Data Area (263) Wd: Word CIO, G, A, DM RRNL Wd Variations ↑RRNL(263) Description When the execution condition is OFF, RRNL(263) is not executed. When the ex- ecution condition is ON, RRNL(263) shifts all bits previously in Wd and Wd+1 to the right, and bit 00 of Wd is shifted into both bit 15 of Wd+1 and into CY.

  • Page 178: One Digit Shift Left: Sld(068)

    Section 5-14 Shift Instructions 5-14-23 ONE DIGIT SHIFT LEFT: SLD(068) Ladder Symbol Operand Data Areas (068) St: Starting word CIO, G, A, DM E: End word CIO, G, A, DM Variations j SLD(068) Description When the execution condition is OFF, SLD(068) is not executed. When the ex- ecution condition is ON, SLD(068) shifts data between St and E (inclusive) by one digit (four bits) to the left.

  • Page 179: One Digit Shift Right: Srd(069)

    Section 5-14 Shift Instructions 5-14-24 ONE DIGIT SHIFT RIGHT: SRD(069) Ladder Symbol Operand Data Areas (069) St: Starting word CIO, G, A, DM E: End word CIO, G, A, DM Variations j SRD(069) Description When the execution condition is OFF, SRD(069) is not executed. When the ex- ecution condition is ON, SRD(069) shifts data between St and E (inclusive) by one digit (four bits) to the right.

  • Page 180: Data Movement Instructions

    Section 5-15 Data Movement Instructions 5-15 Data Movement Instructions Data Movement Instructions are used for moving data between different ad- dresses in data areas. These movements can be programmed to be within the same data area or between different data areas. Data movement is essential for utilizing all of the data areas of the PC.

  • Page 181: Move Not: Mvn(031)

    Section 5-15 Data Movement Instructions Before After execution execution D00100 D00100 0005 0005 5-15-2 MOVE NOT: MVN(031) Ladder Symbol Operand Data Areas (031) S: Source CIO, G, A, T, C, #, DM, DR, IR D: Destination CIO, G, A, T, C, DM, DR, IR Variations j MVN(031) Description...

  • Page 182: Double Move: Movl(032)

    Section 5-15 Data Movement Instructions 5-15-3 DOUBLE MOVE: MOVL(032) Ladder Symbol Operand Data Areas (032) S: Source CIO, G, A, T, C, #, DM MOVL D: Destination CIO, G, A, T, C, DM Variations j MOVL(032) Description When the execution condition is OFF, MOVL(032) is not executed. When the ex- ecution condition is ON, MOVL(032) copies the content of S and S+1 to D and D+1.

  • Page 183: Double Move Not: Mvnl(033)

    Section 5-15 Data Movement Instructions 5-15-4 DOUBLE MOVE NOT: MVNL(033) Ladder Symbol Operand Data Areas (033) S: Source CIO, G, A, T, C, #, DM MVNL D: Destination CIO, G, A, T, C, DM Variations j MVNL(033) Description When the execution condition is OFF, MVNL(033) is not executed. When the ex- ecution condition is ON, MVNL(033) transfers the complement of the content of S and S+1 (specified words or eight-digit hexadecimal constant) to D and D+1, i.e., for each ON bit in S and S+1, the corresponding bit in D and D+1 is turned...

  • Page 184: Data Exchange: Xchg(034)

    Section 5-15 Data Movement Instructions 5-15-5 DATA EXCHANGE: XCHG(034) Ladder Symbol Operand Data Areas (034) Exchange word CIO, G, A, T, C, DM, DR, IR XCHG E Exchange word CIO, G, A, T, C, DM, DR, IR Variations j XCHG(034) Description When the execution condition is OFF, XCHG(034) is not executed.

  • Page 185: Double Data Exchange: Xcgl(035)

    Section 5-15 Data Movement Instructions 5-15-6 DOUBLE DATA EXCHANGE: XCGL(035) Ladder Symbol Operand Data Areas (035) Exchange word CIO, G, A, T, C, DM XCGL E Exchange word CIO, G, A, T, C, DM Variations j XCGL(035) Description When the execution condition is OFF, XCGL(035) is not executed. When the ex- ecution condition is ON, XCGL(035) exchanges the content of E and E +1 with...

  • Page 186: Move To Register: Movr(036)

    Section 5-15 Data Movement Instructions 5-15-7 MOVE TO REGISTER: MOVR(036) Ladder Symbol Operand Data Areas (036) S: Source CIO, G, A, T, C, DM MOVR D: Destination Variations j MOVR(036) Description When the execution condition is OFF, MOVR(036) is not executed. When the execution condition is ON, MOVR(036) copies the PC memory address of word or bit S to the index register designated in D.
  • Page 187 Section 5-15 Data Movement Instructions 5-15-8 MOVE QUICK: MOVQ(037) Ladder Symbol Operand Data Areas (037) S: Source CIO, G, A, T, C, # MOVQ D: Destination CIO, G, A, T, C Description When the execution condition is OFF, MOVQ(037) is not executed. When the execution condition is ON, MOVQ(037) copies the content of S to D at high speed.

  • Page 188: Multiple Bit Transfer: Xfrb(038)

    Section 5-15 Data Movement Instructions 5-15-9 MULTIPLE BIT TRANSFER: XFRB(038) Ladder Symbol Operand Data Areas C: Control word CIO, G, A, T, C, #, DM, DR, IR XFRB C S D S: First source word CIO, G, A, T, C, DM D: First destination word CIO, G, A, DM Variations...
  • Page 189 Section 5-15 Data Movement Instructions Example 1 When CIO 000000 is ON in the following example, eight bits from D00200 (be- ginning with bit 04) will be transferred to D00500 (beginning with bit 08), accord- ing to the contents of D00100. 0000 Address Instruction Operands...

  • Page 190: Block Transfer: Xfer(040)

    Section 5-15 Data Movement Instructions 5-15-10 BLOCK TRANSFER: XFER(040) Ladder Symbol Operand Data Areas (040) N: Number of words CIO, G, A, T, C, #, DM, DR, IR XFER S: 1 source word CIO, G, A, T, C, DM Variations D: 1 destination word CIO, G, A, T, C, DM j XFER(040)

  • Page 191: Block Set: Bset(041)

    Section 5-15 Data Movement Instructions 5-15-11 BLOCK SET: BSET(041) Ladder Symbol Operand Data Areas (041) S: Source word CIO, G, A, T, C, #, DM, DR, IR BSET St: Starting word CIO, G, A, T, C, DM Variations E: End word CIO, G, A, T, C, DM j BSET(041) Description...

  • Page 192: Move Bit: Movb(042)

    Section 5-15 Data Movement Instructions Example The following example shows how to use BSET(041) to change the PV of a timer depending on the status of CIO 000003 and CIO 000004. When CIO 000003 is ON, TIM 0010 will operate as a 50-second timer; when CIO 000004 is ON, TIM 0010 will operate as a 30-second timer.
  • Page 193 Section 5-15 Data Movement Instructions Example When CIO 000000 is ON in the following example, the content of bit 02 of the transfer source word (D00000) is copied to bit 12 of the transfer destination word (CIO 0005) as specified by the contents (1202) of control word (CIO 0035). 0000 Address Instruction...

  • Page 194: Move Digit: Movd(043)

    Section 5-15 Data Movement Instructions 5-15-13 MOVE DIGIT: MOVD(043) Ladder Symbol Operand Data Areas (043) S: Source word CIO, G, A, T, C, #, DM, DR, IR MOVD Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations D: Destination word CIO, G, A, T, C, DM, DR, IR...

  • Page 195: Single Word Distribute: Dist(044)

    Section 5-15 Data Movement Instructions C : #0201 First digit in S: Number of digits: 1 digit First digit in D: S : D00000 D : D00003 5-15-14 SINGLE WORD DISTRIBUTE: DIST(044) Ladder Symbol Operand Data Areas (044) S: Source data CIO, G, A, T, C, #, DM, DR, IR DIST DBs: Destination base CIO, G, A, T, C, DM...

  • Page 196: Data Collect: Coll(045)

    Section 5-15 Data Movement Instructions Before After execution execution CIO 0002 CIO 0002 CIO 0030 CIO 0030 D00410 D00410 5-15-15 DATA COLLECT: COLL(045) Ladder Symbol Operand Data Areas (045) SBs: Source base CIO, G, A, T, C, DM COLL SBs Of: Offset data CIO, G, A, T, C, #, DM, DR, IR Variations...

  • Page 197: Interbank Block Transfer: Bxfr(046)

    Section 5-15 Data Movement Instructions 5-15-16 INTERBANK BLOCK TRANSFER: BXFR(046) Ladder Symbol Operand Data Areas (046) C: First control word CIO, G, A, T, C, DM BXFR C S D S: First source word CIO, G, A, T, C, DM D: First destination word CIO, G, A, T, C, DM Variations...

  • Page 198: Comparison Instructions

    EQU(025). Intermediate instructions are entered between conditions or be- tween a condition and a right-hand instruction. Intermediate instructions cannot be placed at the end of an instruction. CVM1D CPUs are equipped with a similar non-intermediate instruction: CMP(028). Precautions When comparing a value to the PV of a timer or counter, the value must be in...
  • Page 199 Section 5-16 Comparison Instructions Placing other instructions between CMP(020) and the operation which ac- cesses the EQ, LE, and GR Flags may change the status of these flags. Be sure to access them before the desired status is changed. Note Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD.

  • Page 200: Double Compare: Cmpl(021)

    Intermediate instructions cannot be placed at the end of an instruc- tion line. CVM1D CPUs are equipped with a similar non-intermediate instruction: CMPL(029). Constants are expressed in eight digits.

  • Page 201: Block Compare: Bcmp(022)

    Section 5-16 Comparison Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): GR (A50005): Cp1+1 and Cp1 is greater than Cp2+1 and Cp2. EQ (A50006): Cp1+1 and Cp1 equals Cp2+1 and Cp2. LE (A50007): Cp1+1 and Cp1 is less than Cp2+1 and Cp2.
  • Page 202 Section 5-16 Comparison Instructions CB+24 ≤( S ≤( CB+25 Bit 12 CB+26 ≤( S ≤( CB+27 Bit 13 CB+28 ≤( S ≤( CB+29 Bit 14 CB+30 ≤( S ≤( CB+31 Bit 15 Precautions Each lower limit word in the comparison block must be less than or equal to the upper limit.
  • Page 203 Section 5-16 Comparison Instructions 5-16-4 TABLE COMPARE: TCMP(023) Ladder Symbol Operand Data Areas (023) S: Source data CIO, G, A, T, C, #, DM, DR, IR TCMP TB: 1 table word CIO, G, A, T, C, DM Variations R: Result word CIO, G, A, T, C, DM, DR, IR j TCMP(023) Description...

  • Page 204: Multiple Compare: Mcmp(024)

    Section 5-16 Comparison Instructions 5-16-5 MULTIPLE COMPARE: MCMP(024) Ladder Symbol Operand Data Areas (024) table word CIO, G, A, T, C, DM MCMP TB table word CIO, G, A, T, C, DM Variations R: Result word CIO, G, A, DM, DR, IR j MCMP(024) Description When the execution condition is OFF, MCMP(024) is not executed.

  • Page 205: Equal: Equ(025)

    Section 5-16 Comparison Instructions 5-16-6 EQUAL: EQU(025) Ladder Symbol Operand Data Areas (025) compare word CIO, G, A, T, C, #, DM, DR, IR EQU Cp compare word CIO, G, A, T, C, #, DM, DR, IR Variations j EQU(025) Description When the execution condition is OFF, EQU(025) is not executed.

  • Page 206: Input Comparison Instructions (300 To 328)

    Section 5-16 Comparison Instructions Example When CIO 000000 is ON in the following example, the content of CIO 0010 is compared to the content of D05000 and MOV(030) and INC(090) are executed only if the contents are the same. 0000 Address Instruction Operands (025)
  • Page 207 Section 5-16 Comparison Instructions Code Mnemonic Name Function ≠ S TRUE WHEN S <> NOT EQUAL <>L DOUBLE NOT EQUAL <>S SIGNED NOT EQUAL <>SL DOUBLE SIGNED NOT EQUAL TRUE WHEN S < S < LESS THAN <L DOUBLE LESS THAN <S SIGNED LESS THAN <SL...

  • Page 208: Signed Binary Compare: Cps(026)

    Section 5-16 Comparison Instructions When CIO 000001 is OFF, CIO 005001 is turned OFF. 0000 0050 Address Instruction Operands (310) 00000 000000 < D00100 D00200 00001 <(310) 0000 0050 (312) D00100 <S D00110 D00210 D00200 00002 000001 00003 <S(312) D00110 D00210 Comparison : D00100...

  • Page 209: Double Signed Binary Compare: Cpsl(027)

    Section 5-16 Comparison Instructions 5-16-9 DOUBLE SIGNED BINARY COMPARE: CPSL(027) Ladder Symbol Operand Data Areas : First comparison word 1 CIO, G, A, T, C, #, DM, CPSL S : First comparison word 2 CIO, G, A, T, C, #, DM, Description When the execution condition is OFF, CPSL(027) is not executed.

  • Page 210: Unsigned Compare: Cmp(028)

    Section 5-16 Comparison Instructions 5-16-10 UNSIGNED COMPARE: CMP(028) Ladder Symbol Operand Data Areas : Comparison word 1 CIO, G, A, T, C, #, DM, DR, IR CMP S : Comparison word 2 CIO, G, A, T, C, #, DM, DR, IR Variations ! CMP(028) Description...
  • Page 211 Section 5-16 Comparison Instructions • If the content of CIO 0011 and CIO 0010 is equal to that of CIO 0009 and CIO 0008, then output CIO 002001 will turn ON. • If the content of CIO 0011 and CIO 0010 is less than that of CIO 0009 and CIO 0008, then output CIO 002002 will turn ON.

  • Page 212: Conversion Instructions

    Section 5-17 Conversion Instructions 5-17 Conversion Instructions The Conversion Instructions convert word data that is in one format into another format and output the converted data to specified result word(s). All of these instructions change only the content of the words to which converted data is be- ing moved, i.e., the content of source words is the same before and after execu- tion of any of the conversion instructions.

  • Page 213: Binary-To-Bcd: Bcd(101)

    Section 5-17 Conversion Instructions The bit contents of words D00010 and D00011 after execution are: D00010 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 D00011 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 5-17-2 BINARY-TO-BCD: BCD(101) Ladder Symbol Operand Data Areas...

  • Page 214: Double Bcd-To-Double Binary: Binl(102)

    Section 5-17 Conversion Instructions Before After execution execution D00150 D00150 D00160 D00160 The bit contents of words D00150 and D00160 after execution are: D00150 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D00160 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 5-17-3 DOUBLE BCD-TO-DOUBLE BINARY: BINL(102)

  • Page 215: Double Binary-To-Double Bcd: Bcdl(103)

    Section 5-17 Conversion Instructions S+1: CIO 0011 S: CIO 0010 200050=3X16 +13X16 +7X16 +2X16 R+1: D00201 R: D00200 5-17-4 DOUBLE BINARY-TO-DOUBLE BCD: BCDL(103) Ladder Symbol Operand Data Areas (103) S: Source word CIO, G, A, T, C, DM BCDL R: Result word CIO, G, A, DM Variations j BCDL(103)

  • Page 216: 2'S Complement: Neg(104)

    Section 5-17 Conversion Instructions S+1: CIO 0011 S: CIO 0010 2X16 +13X16 +3X16 +2X16 +10=2961930 R+1: D00101 R: D00100 5-17-5 2’S COMPLEMENT: NEG(104) Ladder Symbol Operand Data Areas (104) S: Source word CIO, G, A, T, C, #, DM, DR, IR R: Result word CIO, G, A, DM, DR, IR Variations...

  • Page 217: Double 2'S Complement: Negl(105)

    Section 5-17 Conversion Instructions 5-17-6 DOUBLE 2’S COMPLEMENT: NEGL(105) Ladder Symbol Operand Data Areas (105) S: 1 source word CIO, G, A, T, C, #, DM NEGL R: 1 result word CIO, G, A, DM Variations j NEGL(105) Description When the execution condition is OFF, NEGL(105) is not executed. When the execution condition is ON, NEGL(105) converts the 8-digit hexadecimal content of the source words (S and S+1) to its 2’s complement and outputs the result to the result words (R and R+1).

  • Page 218: Sign: Sign(106)

    Section 5-17 Conversion Instructions 5-17-7 SIGN: SIGN(106) Ladder Symbol Operand Data Areas (106) S: Source word CIO, G, A, T, C, #, DM, DR, IR SIGN R: 1 result word CIO, G, A, DM Variations j SIGN(106) Description When the execution condition is OFF, SIGN(106) is not executed. When the execution condition is ON, SIGN(106) copies the 4-digit signed binary source word (S) to R, extracts the sign from bit 15 of S, and outputs the result to R+1.

  • Page 219: Data Decoder: Mlpx(110)

    Section 5-17 Conversion Instructions 5-17-8 DATA DECODER: MLPX(110) Ladder Symbol Operand Data Areas (110) S: Source word CIO, G, A, T, C, DM, DR, IR MLPX Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations R: 1 result word CIO, G, A, DM j MLPX(110)
  • Page 220 Section 5-17 Conversion Instructions Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to be converted 4-to-16: 0 to 3 8-to-256: 0 or 1 Number of digits to be converted 4-to-16: 0 to 3 (1 to 4 digits) 8-to-256: 0 or 1 (1 or 2 digits) Process...
  • Page 221 Section 5-17 Conversion Instructions Example When CIO 000000 is ON in the following example, three digits of data from CIO 0020 is converted to bit positions and the corresponding bits in three con- secutive words starting with D 00100 are turned ON to indicate the position of the ON bits.
  • Page 222 Section 5-17 Conversion Instructions For 16-bit conversion, DMPX(111) determines the position of the highest ON bit in SB, encodes it into one-digit hexadecimal value corresponding to the bit num- ber of the highest ON bit, then transfers the hexadecimal value to the specified 4-bit digit in R.
  • Page 223 Section 5-17 Conversion Instructions Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to receive converted data 16-to-4: 0 to 3 256-to-8: 0 or 1 Number of digits to be converted 16-to-4: 0 to 3 (1 to 4 digits) 256-to-8: 0 or 1 (1 or 2 digits) Encoding bit...

  • Page 224: 7-Segment Decoder: Sdec(112)

    Section 5-17 Conversion Instructions Example When CIO 000000 is ON in the following example, the bit positions of the highest ON bits in CIO 0010 and 0011 are written to the first two digits of CIO 0020 and the bit positions of the highest ON bits in CIO 0015 and CIO 0016 are written to the last two digits of 0020.
  • Page 225 Section 5-17 Conversion Instructions Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to receive converted data (0 to 3). Number of digits to be converted (0 to 3) 0: 1 digit 1: 2 digits 2: 3 digits...
  • Page 226 Section 5-17 Conversion Instructions Example The following example shows the data to produce data for an “8.” The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexa- decimal digits.

  • Page 227: Ascii Convert: Asc(113)

    Section 5-17 Conversion Instructions 5-17-11 ASCII CONVERT: ASC(113) Ladder Symbol Operand Data Areas (113) S: Source word CIO, G, A, T, C, DM, DR, IR Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations D: 1 destination word CIO, G, A, DM j ASC(113) Description...
  • Page 228 Section 5-17 Conversion Instructions Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below. Di: 0011 Di: 0030 1st half 1st half 2nd half 2nd half 1st half 2nd half Di: 0112 Di: 0130 1st half 1st half...

  • Page 229: Bit Counter: Bcnt(114)

    Section 5-17 Conversion Instructions Di : #0000 0 0 0 0 Convert from digit 0. Convert 1 digit. Output to leftmost bits. No parity. S: D00010 D: CIO 0001 000100 000101 000102 000103 000104 000105 000106 000107 000108 000109 000110 000111 000112 000113...

  • Page 230: Column To Line: Line(115)

    Section 5-17 Conversion Instructions Example When CIO 000007 is ON in the following example, all ON bits in D00030 and D00031 are counted and the results is placed in D00040. 0000 Address Instruction Operands (114) BCNT #0002 D00030 D00040 00000 000007 00001 BCNT(114)

  • Page 231: Line To Column: Colm(116)

    Section 5-17 Conversion Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): The bit designator Bi is not BCD, or it is specifying a non-ex- istent bit (i.e., bit specification must be between 00 and 15). EQ (A50006): Content of D is 0 after execution Example...

  • Page 232: Ascii To Hex: Hex(117)

    Section 5-17 Conversion Instructions Example When CIO 000000 is ON in the following example, the status of bits 00 to 15 in D00005 are copied consecutively to bits number 08 of D00010 through D00025, with the status of bit 00 being transferred to bit 08 of D00010. 0000 Address Instruction Operands...
  • Page 233 Section 5-17 Conversion Instructions Digit Designator Examples The following examples show the digit designators (Di) used to make various multiple-word conversions. Example 1 Di Word Contents Word S+1 Word S Leftmost 8 bits Rightmost 8 bits Leftmost 8 bits Rightmost 8 bits Word D Digit 3 Digit 2...
  • Page 234 Section 5-17 Conversion Instructions 2: Odd The data (8 bits) can only be converted when the number of “1” bits is odd. If the number is even, the Error Flag will turn ON and the data will not be converted. Example “A”...

  • Page 235: Signed Bcd-To-Binary: Bins(275)

    Section 5-17 Conversion Instructions Parity bits: Even 1 1 0 0 0 0 1 1 1 0 1 1 1 0 0 0 First ASCII data to be converted: Rightmost 8 bits Converted to binary data First digit to receive converted data: 1 : Not changed.
  • Page 236 Section 5-17 Conversion Instructions When C = 0002 (Input Data Range: –999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative (–) A to E: Error When C = 0003 (Input Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (–1)

  • Page 237: Signed Binary-To-Bcd: Bcds(276)

    Section 5-17 Conversion Instructions Example 2 When CIO 000001 is ON in the following example, first the signed BCD data for- mat and range in D00300 are checked against data control word “0003” (first operand). If the check is okay, the signed BCD data in D00300 is converted to binary and output to D00400.
  • Page 238 Section 5-17 Conversion Instructions When C = 0002 (Output Data Range: –999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative (–) When C = 0003 (Output Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (–1)

  • Page 239: Double Signed Bcd-To-Binary: Bisl(277)

    Section 5-17 Conversion Instructions S: D00300 Signed binary data F A A 7 D: D00400 Signed BCD data A 3 6 9 (–1369) 5-17-18 DOUBLE SIGNED BCD-TO-BINARY: BISL(277) Ladder Symbol Operand Data Areas (277) C: Control word CIO, G, A, T, C, #, DM, BISL C S D S: 1st source word CIO, G, A, T, C, DM,...
  • Page 240 Section 5-17 Conversion Instructions When C = 0003 (Input Data Range: –1999 9999 to 9999 9999 BCD) 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD A: Negative (-1) F: Negative (–) B to E: Error First the signed BCD data format and range in words S+1 and S are checked against the data control word (C).

  • Page 241: Double Signed Binary-To-Bcd: Bdsl(278)

    Section 5-17 Conversion Instructions 5-17-19 DOUBLE SIGNED BINARY-TO-BCD: BDSL(278) Ladder Symbol Operand Data Areas (278) C: Control word CIO, G, A, T, C, #, DM, BDSL C S D S: 1st source word CIO, G, A, T, C, DM, Variations D: 1st destination word CIO, G, A, DM, ↑BDSL(278)

  • Page 242: Bcd Calculation Instructions

    BCD Calculation Instructions The BCD Calculation Instructions perform arithmetic operations on BCD data. The CVM1D CPUs also support BCD symbol math instructions. Refer to 5-20 Symbol Math Instructions for details. STC(078) and CLC(079), which set and clear the carry flag, are included in this group because most of the BCD operations make use of the carry flag (CY) in their results.

  • Page 243: Set Carry: Stc(078)

    When using any of these instructions, use STC(078) and CLC(079) to set and clear the carry flag. CVM1D CPUs support add, subtract, and rotation shift instructions that do not use the carry flag in their operations. These instructions do not require STC(078) and CLC(079), and reduce the number of program steps that are needed.

  • Page 244: Bcd Subtract: Sub(071)

    Section 5-18 BCD Calculation Instructions Example When CIO 000000 is ON in the following example, CY is cleared by CLC(079), the content of CIO 0200 is added to the contents of CIO 0100 and the status of CY, the results is placed in D00100, and then either all zeros or 0001 is moved into D00101 depending on the status of CY (A50004).
  • Page 245 Section 5-18 BCD Calculation Instructions Note Be sure to clear the carry flag with CLC(079) before executing SUB(071) if its previous status is not required, and check the status of CY after doing a subtrac- tion with SUB(071). If CY is ON as a result of executing SUB(071) (i.e., if the re- sult is negative), the result is output as the 10’s complement of the true answer.

  • Page 246: Bcd Multiply: Mul(072)

    Section 5-18 BCD Calculation Instructions Second Subtraction 0000 CIO 0200 –7577 –0 CIO 0200 2423 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON CIO 002100 to indicate that the value held in CIO 0200 is negative. 5-18-5 BCD MULTIPLY: MUL(072) Ladder Symbol Operand Data Areas...

  • Page 247: Bcd Divide: Div(073)

    Section 5-18 BCD Calculation Instructions 5-18-6 BCD DIVIDE: DIV(073) Ladder Symbol Operand Data Areas (073) Dd: Dividend word CIO, G, A, T, C, #, DM, DR, IR Dr: Divisor word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM j DIV(073)

  • Page 248: Double Bcd Add: Addl(074)

    Section 5-18 BCD Calculation Instructions 5-18-7 DOUBLE BCD ADD: ADDL(074) Ladder Symbol Operand Data Areas (074) Au: 1 augend word CIO, G, A, T, C, #, DM ADDL Ad: 1 addend word CIO, G, A, T, C, #, DM Variations R: 1 result word CIO, G, A, DM...

  • Page 249: Double Bcd Subtract: Subl(075)

    Section 5-18 BCD Calculation Instructions 5-18-8 DOUBLE BCD SUBTRACT: SUBL(075) Ladder Symbol Operand Data Areas (075) Mi: 1 minuend word CIO, G, A, T, C, #, DM SUBL Su: 1 subtrahend wordCIO, G, A, T, C, #, DM Variations R: 1 result word CIO, G, A, DM j SUBL(075)

  • Page 250: Double Bcd Multiply: Mull(076)

    Section 5-18 BCD Calculation Instructions Example The following example works much like that for single-word subtraction. In this example, however, the 8-digit number in CIO 0121 and CIO 0120 is subtracted from the 8-digit number in CIO 0201 and CIO 0200 when CIO 000003 is ON, and the result is output to D00101 and D00100.

  • Page 251: Double Bcd Divide: Divl(077)

    Section 5-18 BCD Calculation Instructions Flags ER (A50003): Content of Md, Md+1, Mr, or Mr+1 is not BCD. Content of *DM word is not BCD when set for BCD. EQ (A50006): The result is 0. Example When CIO 000001 is ON in the following example, the 8-digit content of D00005 and D00006 is multiplied by the content of CIO 0005 and CIO 0006 and places the 16-digit result in CIO 0007, CIO 0008, CIO 0009, and CIO 0010.
  • Page 252 Section 5-18 BCD Calculation Instructions Example The following example shows how to use DIVL(77) to calculate the average of 100 four-digit numbers. These numbers are added and divided using the long versions of the instructions so that the answer can be rounded to preserve accu- racy.
  • Page 253 Section 5-18 BCD Calculation Instructions 0000 Address Instruction Operands (041) jBSET #0000 D00101 D00102 00000 000000 "BSET(041) 00001 (030) #000 jMOV #0000 D00000 D00101 (020) D00102 D00000 #0100 "MOV(030) 00002 A500 #0000 (090) D00000 D00000 00003 CMP(020) (030) MOV *D00000 0200 D00000 #0100...

  • Page 254: Binary Calculation Instructions

    Binary Calculation Instructions The Binary Calculation Instructions all perform arithmetic operations on binary (hexadecimal) data. The CVM1D CPUs also support binary symbol math in- structions. Refer to 5-20 Symbol Math Instructions for details. The addition and subtraction instructions include CY in the calculation as well as in the result.

  • Page 255: Binary Subtract: Sbb(081)

    Section 5-19 Binary Calculation Instructions In the following example, A6E2 + 80C5 = 127A7. The result is a five-digit num- ber, so CY (A50004) = 1, and the content of R + 1 becomes 0001. Au: CIO 0010 Ad: D00100 R+1: D01001 R: D01000 Eight-digit binary numbers can be added more quickly and easily using the...
  • Page 256 Section 5-19 Binary Calculation Instructions Example The following example demonstrates the use of SBB(081) in an 8-digit subtrac- tion. In actual practice, 8-digit binary numbers can be subtracted more quickly and easily using the DOUBLE BINARY SUBTRACT: SBBL(085) instruction instead of a combination of SBB(081) instructions. CY is tested following the first two subtractions to see if the result is negative.

  • Page 257: Binary Multiply: Mlb(082)

    Section 5-19 Binary Calculation Instructions In the following example, 20F55A10 – B8A360E3 = 97AE06D3. In the rightmost four-digit subtraction, Su is less than Mi, so CY (A50004) becomes 1, and the result of the leftmost four-digit subtraction is decremented by 1. In the final cal- culations, 0000 –...

  • Page 258: Binary Divide: Dvb(083)

    Section 5-19 Binary Calculation Instructions Note An equivalent symbol math instruction ( * U(422)) is also available. Precautions Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006):...

  • Page 259: Double Binary Add: Adbl(084)

    Section 5-19 Binary Calculation Instructions Example When CIO 000002 is ON in the following example, the four-digit hexadecimal content of CIO 0007 is divided by the four-digit hexadecimal content of D00100. The quotient is stored in D00101 with the remainder stored in D00102. Note If the content of the divisor word D00101 is zero, the Error Flag (bit A50003) is set and the instruction is not executed.

  • Page 260: Double Binary Subtract: Sbbl(085)

    Section 5-19 Binary Calculation Instructions Example The following example shows an 8-digit addition with CY (A50004) used to store the status of the 9 digit. The status of CY would need to be stored in another word (normally D05002) before it was affected by execution of another instruc- tion.
  • Page 261 Section 5-19 Binary Calculation Instructions Precautions Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): CY (A50004): The result is negative. EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R+1.

  • Page 262: Double Binary Divide: Dvbl(087)

    Section 5-19 Binary Calculation Instructions Note An equivalent symbol math instruction ( * UL(423)) is also available. Precautions Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006):...
  • Page 263 Section 5-19 Binary Calculation Instructions Flags ER (A50003): Dr and Dr+1 contain 0. Content of *DM word is not BCD when set for BCD. EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R+1. Example When CIO 000000 is ON in the following example the content of CIO 0100 and CIO 0101 is divided by the content of D00500 and D00501 and the results is out-...

  • Page 264: Symbol Math Instructions

    Section 5-20 Symbol Math Instructions 5-20 Symbol Math Instructions The Symbol Math Instructions perform arithmetic operations on BCD or binary data. 5-20-1 Binary Addition: +(400)/+L(401)/+C(402)/+CL(403) SIGNED BINARY ADD WITHOUT CARRY: +(400) Ladder Symbol Operand Data Areas (400) Au: Augend word CIO, G, A, T, C, #, DM, DR, IR Ad: Addend word CIO, G, A, T, C, #, DM, DR, IR...
  • Page 265 Section 5-20 Symbol Math Instructions DOUBLE SIGNED BINARY ADD WITHOUT CARRY When the execution condition is OFF, +L(401) is not executed. When the execu- tion condition is ON, +L(401) adds the 8-digit contents of Au+1 and Au and the 8-digit contents of Ad+1 and Ad, and places the result in R and R + 1. CY will be set if the result is greater than FFFF FFFF.

  • Page 266: Bcd Addition: +B(404)/ +Bl(405)/+Bc(406)/+Bcl(407)

    Section 5-20 Symbol Math Instructions When Au and Ag are both positive numbers and the addition result is negative, the Overflow Flag (A50009) turns ON. When Au and Ag are both negative num- bers and the addition result is positive, the Underflow Flag (A50010) turns ON. If a addition result in a carry, the Carry Flag turns ON.
  • Page 267 Section 5-20 Symbol Math Instructions Description BCD ADD WITHOUT CARRY When the execution condition is OFF, +B(404) is not executed. When the execu- tion condition is ON, +B(404) adds the contents of Au and Ad and places the re- sult in R. CY will be set if the result is greater than 9999. DOUBLE BCD ADD WITHOUT CARRY When the execution condition is OFF, +BL(405) is not executed.

  • Page 268: Binary Subtraction: -(410)/ -L(411)/-C(412)/-Cl(413)

    Section 5-20 Symbol Math Instructions Example +BL Operation When CIO 000000 is ON in the following example, the contents of D00101 and D00100 are added to the content of D00111 and D00110, and the result is output in eight-digit BCD to D00121 and D00120. +BCL Operation When CIO 000001 is ON in the following example, the contents of D00201 and D00200 are added to the content of D00211 and D00210, and the result includ-...
  • Page 269 Section 5-20 Symbol Math Instructions DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: –CL(413) Ladder Symbol Operand Data Areas (413) Mi: Minuend word CIO, G, A, T, C, #, DM, –CL Su: Subtrahend word CIO, G, A, T, C, #, DM, Variations R: Result word CIO, G, A, DM, j –CL(413)
  • Page 270 Section 5-20 Symbol Math Instructions Flags ER (A50003): The content of a*DM word is not BCD when set for BCD. CY (A50004): The subtraction resulted in a borrow. EQ(A50006) The contents of word R (or word R and R+1 for “double” instructions) after the subtraction is all zeros N (A50008) The leftmost bit (MSB) of word R (or word R+1 for “double”...
  • Page 271 Section 5-20 Symbol Math Instructions Programming Example 1 –L Operation When CIO 000000 is ON in the following example, the content of D00111 and D00110 is subtracted from the content of D00101 and D00100, and the result is output in eight-digit binary to D00121 and D00120. CY is set if the subtraction resulted in a borrow.
  • Page 272 Section 5-20 Symbol Math Instructions Subtraction at 1 Mi+1: CIO 0201 Mi: CIO 0200 2 0 F 5 Su+1: CIO 0121 Su: CIO 0120 – R+1: D00101 R+1: D00100 F 9 2 D The Carry Flag (A50004) is ON, so the result is subtracted from 0000 0000 to obtain the actual result.

  • Page 273: Bcd Subtraction: -B(414)/ -Bl(415)/-Bc(416)/-Bcl(417)

    Section 5-20 Symbol Math Instructions 5-20-4 BCD Subtraction: –B(414)/ –BL(415)/–BC(416)/–BCL(417) BCD SUBTRACT WITHOUT CARRY: –B(414) Ladder Symbol Operand Data Areas (414) Mi: Minuend word CIO, G, A, T, C, #, DM, DR, IR –B Su: Subtrahend word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR...
  • Page 274 Section 5-20 Symbol Math Instructions DOUBLE BCD SUBTRACT WITHOUT CARRY When the execution condition is OFF, –BL(415) is not executed. When the execution condition is ON, –BL(415) subtracts the 8-digit BCD content of Su and Su+1 from the 8-digit BCD content in Mi and Mi+1, and places the result in R and R+1.
  • Page 275 Section 5-20 Symbol Math Instructions –BCL Operation When CIO 000001 is ON in the following example, the content of D00211 and D00210 are subtracted from the content of D00201 and D00200, and the result including the carry is output in eight-digit BCD to D00221 and D00220. CY is set if the result is negative Address Instruction Operands...
  • Page 276 Section 5-20 Symbol Math Instructions Subtraction at 1 Mi+1: CIO 0201 Mi: CIO 0200 0 9 5 8 Su+1: CIO 0121 Su: CIO 0120 – 09583960 + (100000000 – 17072641) R+1: D00101 R+1: D00100 9 2 2 5 1 1 3 1 9 The Carry Flag (A50004) is ON, so the result is subtracted from 0000 0000.

  • Page 277: Binary Multiplication: *(420)/ *L(421)/*U(422)/*Ul(423)

    Section 5-20 Symbol Math Instructions 5-20-5 Binary Multiplication: *(420)/ *L(421)/*U(422)/*UL(423) SIGNED BINARY MULTIPLY: *(420) Ladder Symbol Operand Data Areas (420) Md: Multiplicand word CIO, G, A, T, C, #, DM, DR, IR Mr: Multiplier word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM...
  • Page 278 Section 5-20 Symbol Math Instructions DOUBLE SIGNED BINARY MULTIPLY When the execution condition is OFF, *L(421) is not executed. When the execu- tion condition is ON, *L(421) multiplies the signed 8-digit content of Md and Md+1 by the signed content of Mr and Mr+1, and places the result in R to R+3. Md + 1 Mr + 1 R + 3...

  • Page 279: Bcd Multiplication: *B(424)/ *Bl(425)

    Section 5-20 Symbol Math Instructions *UL Operation When CIO 000001 is ON in the following example, the content of D00201 and D00200 are multiplied by the content of D00211 and D00210, in eight-digit binary without sign, and the result is output to D00223 through D00220. Address Instruction Operands 0000...
  • Page 280 Section 5-20 Symbol Math Instructions DOUBLE BCD MULTIPLY When the execution condition is OFF, *BL(425) is not executed. When the execution condition is ON, *BL(425) multiplies the 8-digit BCD content of Md and Md+1 by the BCD content of Mr and Mr+1, and places the result in R to R+3. Md + 1 Mr + 1 R + 3...

  • Page 281: Binary Division: /(430)/ /L(431)//U(432)//Ul(433)

    Section 5-20 Symbol Math Instructions 5-20-7 Binary Division: /(430)/ /L(431)//U(432)//UL(433) SIGNED BINARY DIVIDE: /(430) Ladder Symbol Operand Data Areas (430) Dd: Dividend word CIO, G, A, T, C, #, DM, DR, IR Dr: Divisor word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM...
  • Page 282 Section 5-20 Symbol Math Instructions DOUBLE SIGNED BINARY DIVIDE When the execution condition is OFF, /L(431) is not executed. When the execu- tion condition is ON, /L(431) divides the signed 8-digit content of Dd and D+1 by the signed content of Dr and Dr+1 and the result is placed in R to R+3: the quo- tient in R and R+1, and the remainder in R+2 and R+3.

  • Page 283: Bcd Division: /B(434)/ /Bl(435)

    Section 5-20 Symbol Math Instructions /UL Operation When CIO 000001 is ON in the following example, the unsigned content of D00201 and D00200 is divided by the unsigned content of D00211 and D00210, in eight-digit binary. When the result is obtained, the quotient is output to D00221 and D00220, and the remainder is output to D00223 and D00222.
  • Page 284 Section 5-20 Symbol Math Instructions DOUBLE BCD DIVIDE When the execution condition is OFF, /BL(435) is not executed. When the execution condition is ON, the BCD 8-digit content of Dd and D+1 is divided by the BCD content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, and the remainder in R+2 and R+3.

  • Page 285: Floating-Point Math Instructions

    Floating-point Math Instructions Section 5-21 5-21 Floating-point Math Instructions The Floating-point Math Instructions convert data and perform floating-point arithmetic operations. Code Mnemonic Name FIX (*) FLOATING TO 16-BIT FIXL (*) FLOATING TO 32-BIT FLT (*) 16-BIT TO FLOATING FLTL (*) 32-BIT TO FLOATING +F (*) FLOATING-POINT ADD...
  • Page 286 Floating-point Math Instructions Section 5-21 Floating-point Data The following data can be expressed by floating-point data: • –R x value x –1.175494 x 10 –38 • –3.402823 x 10 • 0 x value x 3.402823 x 10 –38 • 1.175494 x 10 •...
  • Page 287 Floating-point Math Instructions Section 5-21 0000 Address Instruction Operands (041) "BSET 00000 000000 #0000 D00100 D00101 "BSET(041) 00001 (100) #0000 D00000 D00200 D00100 D00101 (100) D00001 D00201 00002 BIN(100) D00000 (452) D00200 D00200 D00202 00003 BIN(100) D00001 (452) D00201 D00204 D00201 00004 FLT(425)

  • Page 288: Floating To 16-Bit: Fix(450)

    Floating-point Math Instructions Section 5-21 Calculations Example ) 100 Distance r = Distance r = = 141.4214 –1 –1 Angle θ = tan Angle θ = tan = 45.0 DM Contents D00000 0 1 0 0 D00100 0 1 4 1 θ...

  • Page 289: Floating To 32-Bit: Fixl(451)

    Floating-point Math Instructions Section 5-21 Only the integer portion of the floating-point data is converted, and the fraction portion is truncated. For example, “3.5” becomes “3,” and “–3.5” becomes “–3.” Precautions S must be floating-point data between –32,768 and 32,767. Note Refer to page 101 for general precautions on operand data areas.

  • Page 290: 16-Bit To Floating: Flt(452)

    Floating-point Math Instructions Section 5-21 5-21-3 16-BIT TO FLOATING: FLT(452) Ladder Symbol Operand Data Areas (452) S: Source word CIO, G, A, T, C, #, DM, DR, IR R: First result word CIO, G, A, DM Variations ↑FLT(452) Description When the execution condition OFF, FLT(452) is not executed. When the execu- tion condition is ON, FLT(452) converts the 16-bit binary content of S to 32-bit floating-point data, and places the result in R and R+1.

  • Page 291: Floating-Point Add: +F(454)

    Floating-point Math Instructions Section 5-21 Flags ER (A50003): The content of a*DM word is not BCD when set for BCD. EQ (A50006): The exponent and mantissa of the result are 0. N (A50008): The result of the conversion is a negative number. 5-21-5 FLOATING-POINT ADD: +F(454) Ladder Symbol Operand Data Areas...

  • Page 292: Floating-Point Subtract: -F(455)

    Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-6 FLOATING-POINT SUBTRACT: –F(455) Ladder Symbol Operand Data Areas (455) Mi: First minuend word CIO, G, A, T, C, #, DM –F Su: First subtrahend word CIO, G, A, T, C, #, DM...

  • Page 293: Floating-Point Multiply: *F(456)

    Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-7 FLOATING-POINT MULTIPLY: *F(456) Ladder Symbol Operand Data Areas (456) Md: First multiplicand word CIO, G, A, T, C, #, DM Mr: First multiplier word CIO, G, A, T, C, #, DM Variations...

  • Page 294: Floating-Point Divide: /F(457)

    Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-8 FLOATING-POINT DIVIDE: /F(457) Ladder Symbol Operand Data Areas (457) Dd: First dividend word CIO, G, A, T, C, #, DM Dr: First divisor word CIO, G, A, T, C, #, DM Variations...

  • Page 295: Degrees To Radians: Rad(458)

    Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-9 DEGREES TO RADIANS: RAD(458) Ladder Symbol Operand Data Areas (458) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM...

  • Page 296: Radians To Degrees: Deg(459)

    Floating-point Math Instructions Section 5-21 5-21-10 RADIANS TO DEGREES: DEG(459) Ladder Symbol Operand Data Areas (459) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑RAD(459) Description When the execution condition OFF, DEG(459) is not executed. When the execu- tion condition is ON, DEG(459) converts the 32-floating-point content of S and S+1 from degrees to radians, and places the result in R and R+1.

  • Page 297: Sine: Sin(460)

    Floating-point Math Instructions Section 5-21 5-21-11 SINE: SIN(460) Ladder Symbol Operand Data Areas (460) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑SIN(460) Description When the execution condition OFF, SIN(460) is not executed. When the execu- tion condition is ON, SIN(460) computes the sine of the angle (in radians) ex- pressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.

  • Page 298: Cosine: Cos(461)

    Floating-point Math Instructions Section 5-21 5-21-12 COSINE: COS(461) Ladder Symbol Operand Data Areas (461) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑COS(461) Description When the execution condition OFF, COS(461) is not executed. When the execu- tion condition is ON, COS(461) computes the cosine of the angle (in radians) expressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.

  • Page 299: Tangent: Tan(462)

    Floating-point Math Instructions Section 5-21 5-21-13 TANGENT: TAN(462) Ladder Symbol Operand Data Areas (462) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑TAN(462) Description When the execution condition OFF, TAN(462) is not executed. When the execu- tion condition is ON, TAN(462) computes the tangent of the angle (in radians) expressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.

  • Page 300: Sine To Angle: Asin(463)

    Floating-point Math Instructions Section 5-21 N (A50008): The result is a negative number. OF (A50009): The absolute value of the result is greater than the maximum value that can be expressed for floating-point data. UF (A50010): OFF when the computation is executed. 5-21-14 SINE TO ANGLE: ASIN(463) Ladder Symbol Operand Data Areas...

  • Page 301: Cosine To Angle: Acos(464)

    Floating-point Math Instructions Section 5-21 OF (A50009): OFF when the computation is executed. UF (A50010): OFF when the computation is executed. 5-21-15 COSINE TO ANGLE: ACOS(464) Ladder Symbol Operand Data Areas (464) S: First source word CIO, G, A, T, C, #, DM ACOS R: First result word CIO, G, A, DM...

  • Page 302: Tangent To Angle: Atan(465)

    Floating-point Math Instructions Section 5-21 5-21-16 TANGENT TO ANGLE: ATAN(465) Ladder Symbol Operand Data Areas (465) S: First source word CIO, G, A, T, C, #, DM ATAN R: First result word CIO, G, A, DM Variations ↑ATAN(465) Description When the execution condition OFF, ATAN(465) is not executed. When the execution condition is ON, ATAN(465) computes the angle (in radians) for a tan- gent expressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.

  • Page 303: Square Root: Sqrt(466)

    Floating-point Math Instructions Section 5-21 5-21-17 SQUARE ROOT: SQRT(466) Ladder Symbol Operand Data Areas (466) S: First source word CIO, G, A, T, C, #, DM SQRT R: First result word CIO, G, A, DM Variations ↑SQRT(466) Description When the execution condition OFF, SQRT(466) is not executed. When the execution condition is ON, SQRT(466) computes the square root of the 32-float- ing-point content of S and S+1, and places the result in R and R+1.

  • Page 304: Exponent: Exp(467)

    Floating-point Math Instructions Section 5-21 5-21-18 EXPONENT: EXP(467) Ladder Symbol Operand Data Areas (467) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑EXP(467) Description When the execution condition OFF, EXP(467) is not executed. When the execu- tion condition is ON, EXP(467) computes the exponent for the 32-floating-point content of S and S+1, and places the result in R and R+1.

  • Page 305: Logarithm: Log(468)

    Floating-point Math Instructions Section 5-21 5-21-19 LOGARITHM: LOG(468) Ladder Symbol Operand Data Areas (468) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations ↑LOG(468) Description When the execution condition OFF, LOG(468) is not executed. When the execu- tion condition is ON, LOG(468) computes the natural logarithm for the 32-float- ing-point content of S and S+1, and places the result in R and R+1.

  • Page 306: Increment/Decrement Instructions

    Section 5-22 Increment/Decrement Instructions 5-22 Increment/Decrement Instructions The Increment/Decrement Instructions all either increment or decrement a num- ber by one. The content of the source word is overwritten with the instruction result for all increment/decrement instructions. 5-22-1 INCREMENT BCD: INC(090) Ladder Symbol Operand Data Area (090)

  • Page 307: Increment Binary: Incb(092)

    Section 5-22 Increment/Decrement Instructions Example When CIO 000000 is ON in the following example, the content of D00010 is decremented by 1 as a BCD value. 0000 Address Instruction Operands (091) DEC D00010 00000 000000 00001 DEC(091) D00010 D00010 D00010 –...

  • Page 308: Decrement Binary: Decb(093)

    Section 5-22 Increment/Decrement Instructions 5-22-4 DECREMENT BINARY: DECB(093) Ladder Symbol Operand Data Area (093) Wd: Word CIO, G, A, DM, DR, IR DECB Wd Variations j DECB(093) Description When the execution condition is OFF, DECB(093) is not executed. When the ex- ecution condition is ON, DECB(093) decrements Wd, without affecting carry (CY).

  • Page 309: Double Decrement Bcd: Decl(095)

    Section 5-22 Increment/Decrement Instructions Example When CIO 000000 is ON in the following example, the content of D0100 and D01001 is incremented by 1 as a BCD value. 0000 Address Instruction Operands (094) INCL D01000 00000 000000 00001 INCL(094) D01000 Wd+1: D01001 Wd: D01000 Wd+1: D01001...

  • Page 310: Double Decrement Binary: Dcbl(097)

    Section 5-22 Increment/Decrement Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of Wd+1 after execution. Example When CIO 000000 is ON in the following example, the content of CIO 0500 and CIO 0501 is incremented by 1 as a binary value.

  • Page 311: Special Math Instructions

    Section 5-23 Special Math Instructions 5-23 Special Math Instructions The Special Math Instructions perform special arithmetic operations. MAX(165) searches a range of words for the maximum value. MIN(166) searches a range of words for the minimum value. SUM(167) adds a range of words. ROOT(140) finds the square root of a value.

  • Page 312: Find Minimum: Min(166)

    Section 5-23 Special Math Instructions Example When CIO 000000 is ON in the following example, MAX(165) outputs to D00500 the maximum value within the 10-word range from CIO 0200 to CIO 0209. Be- cause bit 14 of C is ON, the lower address of the two addresses within the range that contain the maximum value is output to IR0.
  • Page 313 Section 5-23 Special Math Instructions When bit 15 of C is OFF, data within the range is treated as unsigned binary and when it is ON the data is treated as signed binary. Refer to 3-2 Data Area Struc- ture for information on signed and unsigned binary data. 15 14 13 12 11 Number of words in range (N)

  • Page 314: Sum: Sum(167)

    Section 5-23 Special Math Instructions 5-23-3 SUM: SUM(167) Ladder Symbol Operand Data Areas (167) C: Control word CIO, G, A, #, DM, DR, IR word in range CIO, G, A, T, C, DM Variations D: 1 destination word CIO, G, A, DM j SUM(167) Description When the execution condition is OFF, SUM(167) is not executed.

  • Page 315: Bcd Square Root: Root(140)

    Section 5-23 Special Math Instructions C : # 1 0 0 Binary Unsigned D00000 3F2A $2000 D00001 51C3 $2001 D00002 E02A $2002 D00003 7C9F $2003 D00004 2A20 $2004 10 words D00005 A827 $2005 D00006 2A20 $2006 D00007 E02A $2007 D00008 C755 $2008 D00009...
  • Page 316 Section 5-23 Special Math Instructions Example The following example shows how to take the square root of a 4-digit number and then round the result. When CIO 000000 is ON, first the words to be used are cleared to all zeros and then the value whose square root is to be taken is moved to Sq+1.

  • Page 317: Binary Root: Rotb(274)

    Section 5-23 Special Math Instructions 5-23-5 BINARY ROOT: ROTB(274) Ladder Symbol Operand Data Areas (274) S: First source word CIO, G, A, T, C, #, DM ROTB R: Result word CIO, G, A, DM, DR, IR Variations ↑ROTB(274) Description When the execution condition is OFF, ROTB(274) is not executed. When the ex- ecution condition is ON, ROTB(274) computes the square root of the 32-bit binary content of the specified word (S) and outputs the integer portion of the result to the specified result word (R).

  • Page 318: Floating Point Divide: Fdiv(141)

    Section 5-23 Special Math Instructions 5-23-6 FLOATING POINT DIVIDE: FDIV(141) Ladder Symbol Operand Data Areas (141) Dd: 1 dividend word CIO, G, A, T, C, DM FDIV Dr: 1 divisor word CIO, G, A, T, C, DM Variations R: 1 result word CIO, G, A, DM j FDIV(141)
  • Page 319 Section 5-23 Special Math Instructions First the original numbers must be placed in floating-point form. Because the numbers are originally without decimal points, the exponent will be 4 (e.g., 3452 would equal 0.3452 x 10 ). All of the moves are to place the proper data into con- secutive words for the final division, including the exponent and zeros.

  • Page 320: Arithmetic Process: Apr(142)

    Section 5-23 Special Math Instructions 5-23-7 ARITHMETIC PROCESS: APR(142) Ladder Symbol Operand Data Areas (142) C: Control word CIO, G, A, #, DM, DR, IR S: Source data CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR j APR(142) Description...
  • Page 321 Section 5-23 Special Math Instructions Source data Result S: D00010 R: D00200 –1 –1 –2 –3 –4 Result data has four significant Enter input data not exceeding #0900 digits, fifth in BCD form. and higher digits are ignored. The result for cos(0) will be 0.9999, not 1.

  • Page 322: Pid And Related Instructions

    Section 5-24 PID and Related Instructions Content Coordinate 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 D00000 $C00B D00001 $0000 (m–1 = 11: 12 line D00002 $0000 segments) D00003 $0005 D00004 $0F00 Output and D00005 $001A...
  • Page 323 Section 5-24 PID and Related Instructions If the manipulated variable after the PID action exceeds the upper limit, the Greater Than (>) Flag (A50005) will turn ON and the result will be output at the upper limit. If the manipulated variable after the PID action is less than the lower limit, the Less Than (<) Flag (A50007) will turn ON and the result will be output at the lower limit.
  • Page 324 Section 5-24 PID and Related Instructions Item Contents Setting range 0: 8 bits 5: 13 bits Input range The number of input data bits. 1: 9 bits 1: 9 bits 6: 14 bits 6: 14 bits Output range The number of output data bits. {The number 2: 10 bits 7: 15 bits of output bits is automatically the same as the...
  • Page 325 Section 5-24 PID and Related Instructions PID Control Method PID control actions are executed by means of PID control with feed-forward con- trol (two degrees of freedom). When overshooting is prevented with simple PID control, stabilization of distur- bances is slowed (1). If stabilization of disturbances is speeded up, on the other hand, overshooting occurs and response toward the target value is slowed (2).
  • Page 326 Section 5-24 PID and Related Instructions Integral Action (I) Combining integral action with proportional action reduces the offset according to the time that has passed. The strength of the integral action is indicated by the integral time, which is the time required for the manipulated variable of the inte- gral action to reach the same level as the manipulated variable of the proportion- al action with respect to the step deviation, as shown in the following illustration.
  • Page 327 Section 5-24 PID and Related Instructions The strength of the derivative action is indicated by the derivative time, which is the time required for the manipulated variable of the derivative action to reach the same level as the manipulated variable of the proportional action with re- spect to the step deviation, as shown in the following illustration.
  • Page 328 Section 5-24 PID and Related Instructions • Forward action: MV is increased when the PV is larger than the SV. • Reverse action: MV is increased when the PV is smaller than the SV. Reverse Action Forward Action Proportional Proportional band band 100%...
  • Page 329 Section 5-24 PID and Related Instructions Precautions PID data must be within prescribed ranges. Note Refer to page 101 for general precautions on operand data areas. Flags ER (A50003): PID data is outside of the allowable range. The actual sampling period is two or more times the sam- pling period that has been set.
  • Page 330 Section 5-24 PID and Related Instructions Control Data Settings Address Value Contents Parameters for D01000 C001 Binary/f(x)=f(S)/ APR instruction 1 No. of coordinates D01001 1770 Max. X value D01002 0000 D01003 1770 D01004 FFFF Parameters for D01500 C001 Binary/f(x)=f(S)/ APR instruction 2 No.

  • Page 331: Limit Control: Lmt(271)

    Section 5-24 PID and Related Instructions 5-24-2 LIMIT CONTROL: LMT(271) Ladder Symbol Operand Data Areas (271) S: Input word CIO, G, A, T, C, #, DM, DR, IR C: First limit word CIO, G, A, T, C, DM Variations D: Output word CIO, G, A, T, C, DM, DR, IR ↑LMT(271) Description...

  • Page 332: Dead-Band Control: Band(272)

    Section 5-24 PID and Related Instructions 0000 Address Instruction Operands (271) 00000 000000 LMT 0001 D00100 D00110 00001 LMT(271) 0001 D00100 D00110 CIO 0001 D00101 D00100 CIO 0001 D00101 D00100 41F5 4FFF E325 78CC 4FFF E325 78CC > 4FFF D00110 E325 <...

  • Page 333: Dead-Zone Control: Zone(273)

    Section 5-24 PID and Related Instructions Precautions The lower limit (C) must be less than or equal to the upper limit (C+1). Note Refer to page 101 for general precautions on operand data areas. Flags ER (A50003): The upper limit setting is less than the lower limit. The content of a*DM word is not BCD when set for BCD.
  • Page 334 Section 5-24 PID and Related Instructions If the input data (S) is greater than zero, the input data plus the positive bias will be output to D and the Greater Than Flag (A50005) will turn ON. If the input data (S) is equal to zero, 0000 will be output to D and the Equals Flag (A50006) will turn ON.

  • Page 335: Logic Instructions

    Section 5-25 Logic Instructions 5-25 Logic Instructions The logic instructions perform logic operations on word data. 5-25-1 LOGICAL AND: ANDW(130) Ladder Symbol Operand Data Areas (130) : Input 1 CIO, G, A, T, C, #, DM, DR, IR ANDW : Input 2 CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word...
  • Page 336 Section 5-25 Logic Instructions 5-25-2 LOGICAL OR: ORW(131) Ladder Symbol Operand Data Areas (131) : Input 1 CIO, G, A, T, C, #, DM, DR, IR : Input 2 CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR j ORW(131) Description...

  • Page 337: Exclusive Nor: Xnrw(133)

    Section 5-25 Logic Instructions Precautions Refer to page 101 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R after execution. Example When CIO 000000 is ON in the following example, the logical exclusive OR is taken of corresponding bits in CIO 0010 and CIO 0020 and the results is placed...
  • Page 338 Section 5-25 Logic Instructions CIO 0010 CIO 0020 D00200 5-25-5 DOUBLE LOGICAL AND: ANDL(134) Ladder Symbol Operand Data Areas (134) : Input 1 CIO, G, A, T, C, #, DM ANDL : Input 2 CIO, G, A, T, C, #, DM Variations R: Result word CIO, G, A, DM...
  • Page 339 Section 5-25 Logic Instructions 5-25-6 DOUBLE LOGICAL OR: ORWL(135) Ladder Symbol Operand Data Areas (135) : Input 1 CIO, G, A, T, C, #, DM ORWL : Input 2 CIO, G, A, T, C, #, DM Variations R: Result word CIO, G, A, DM j ORWL(135) Description...

  • Page 340: Double Exclusive Nor: Xnrl(137)

    Section 5-25 Logic Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R+1 after execution. Example When CIO 000000 is ON in the following example, the logical exclusive OR is taken of corresponding bits in CIO 0010 to CIO 0011 and CIO 0020 to CIO 0020 and the results is placed in corresponding bits of D00200 and D00201.

  • Page 341: Complement: Com(138)

    Section 5-25 Logic Instructions CIO 0011 CIO 0010 CIO 0021 CIO 0020 D00201 D00200 5-25-9 COMPLEMENT: COM(138) Ladder Symbol Operand Data Area (138) Wd: Word CIO, G, A, DM, DR, IR COM Wd Variations j COM(138) Description When the execution condition is OFF, COM(138) is not executed. When the ex- ecution condition is ON, COM(138) turns OFF all ON bits and turns ON all OFF bits in Wd.

  • Page 342: Double Complement: Coml(139)

    Section 5-26 Time Instructions 5-25-10 DOUBLE COMPLEMENT: COML(139) Ladder Symbol Operand Data Area (139) Wd: Word CIO, G, A, DM COML Wd Variations j COML(139) Description When the execution condition is OFF, COML(139) is not executed. When the execution condition is ON, COML(139) turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1.

  • Page 343: Seconds To Hours: Hms(144)

    Section 5-26 Time Instructions For the source data, the seconds are designated in bits 00 through 07 and the minutes are designated in bits 08 through 15 of S. The hours are designated in S+1. The maximum is thus 9,999 hours, 59 minutes, and 59 seconds. The results are output to R and R+1.

  • Page 344: Calendar Add: Cadd(145)

    Section 5-26 Time Instructions Example When CIO 000000 is OFF in the following example, the following instruction would convert the seconds given in D00000 and D00001 to hours, minutes, and seconds and store the results in D00100 and D00101 as shown. 0000 Address Instruction Operands...

  • Page 345: Calendar Subtract: Csub(146)

    Section 5-26 Time Instructions Example When CIO 000000 is ON in the following example, the time data in D02000 and D02001 is added to the calender data in D01000 through D01002 and output as calender data to D03000 through D03002. 0000 Address Instruction Operands...

  • Page 346: Clock Compensation: Date(179)

    Section 5-26 Time Instructions Precautions C, C+1, C+2, T, and T+1 must be BCD and in the proper format. Note Refer to page 101 for general precautions on operand data areas. Flags ER (A50003): Time or calendar data is not in the correct format (including impossible dates such as Feb.

  • Page 347: Special Instructions

    Section 5-27 Special Instructions Word 15 to 08 07 to 00 Minute (00 to 59) Second (00 to 59) (01 to 31) Hour (00 to 23) Year (00 to 99)* Month (01 to 12) (00 to 06) 00: Sunday 01: Monday 02: Tuesday 03: Wednesday 04: Thursday...
  • Page 348 FAL(006) and FALS(007)), the new error code will replace the previous one. The system also outputs error codes to A400. Refer to Section 6 Trouble- shooting in the CVM1D PCs Installation Guide for details on error code priority. FAL number...

  • Page 349: Failure Point Detection: Fpd(177)

    Section 5-27 Special Instructions If M designates the first word in a table containing a message, it cannot be one of the last seven words in a data area. FAL(006) and FALS(007) share FAL numbers. If two instructions use the same FAL number, only the first instruction using the FAL number Will be recognized.
  • Page 350 Section 5-27 Special Instructions the input in the instruction block that is preventing an output from being turned FPD(177) can be used in the program as many times as desired, but each must use a different D even if the same message is being output. The following diagram illustrates the type of program section that can be diag- nosed with FPD(177).
  • Page 351 Section 5-27 Special Instructions rectly through index registers, however, are not examined. If more than one in- put condition is OFF, the input condition on the highest instruction line and near- est the left bus bar is selected. When IR 00000 to IR 00003 are ON in the following example, the normally closed condition IR 00002 would be found as the cause of the diagnostic output not turning ON.
  • Page 352 Section 5-27 Special Instructions Words D+1 to D+8 contain information in ASCII displayed on a Program- ming Device along with the bit address when FPD(177) is executed. Words D+5 to D+8 contain the message preset by the user as shown in the follow- ing table.
  • Page 353 Section 5-27 Special Instructions In the following example, it is assumed that CIO 000001 through CIO 000004 are all ON, thus CIO 000003 is output as the address of the bit responsible for CIO 002000 not turning ON. A500 Address Instruction Operands First Scan Flag (030)

  • Page 354: Maximum Cycle Time Extend: Wdt(178)

    Section 5-27 Special Instructions 5-27-3 MAXIMUM CYCLE TIME EXTEND: WDT(178) Ladder Symbol Operand Data Area (178) T: Timer value # (0000 to 3999) Variations j WDT(178) Generally, the maximum cycle time is designated in the PC Setup, and if the cycle time exceeds the designated value, a fatal error (Cycle Time Too Long) will occur.

  • Page 355: I/O Refresh: Iorf(184)

    Section 5-27 Special Instructions 5-27-4 I/O REFRESH: IORF(184) Ladder Symbol Operand Data Areas (184) St: Starting word IORF E: Ending word Variations j IORF(184) Description When the execution condition is OFF, IORF(184) is not executed. When the ex- ecution condition is ON, all words between St and E will be refreshed. This will be in addition to the normal I/O refresh performed during the CPU’s scan.
  • Page 356 Section 5-27 Special Instructions Bits 00 to 06 specify the Unit to which the characters will be output (specifics are shown in the following diagram). Bit 07 determines whether the source data is hexadecimal (OFF) or 7-segment display code (ON). Bit 08 determines whether the characters will flash (ON) or not (OFF).
  • Page 357 Section 5-27 Special Instructions D15000 Rack no. 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 Rack no. 2 Set to 0 Set to 0 I/O Interface Unit Rack no. 1 RT address 0 Segment specified Blinking indication Automatic indication...

  • Page 358: Data Search: Srch(164)

    Section 5-27 Special Instructions Example When CIO 000000 is ON in the following example, the current EM bank is changed to bank 3. The contents of A511 would change to “8003” to indicate that bank 3 is the current bank. 0000 Address Instruction...
  • Page 359 Section 5-28 Flag/Register Instructions Wd 0500 89AB Memory address D00000 1234 $2000 D00001 5678 $2001 D00002 ABCD $2002 D00003 EF13 $2003 D00004 89AB $2004 Same data 10 words D00005 8860 $2005 D00006 90CD $2006 D00007 00FF $2007 D00008 89AB $2008 Same data D00009 810C $2009...

  • Page 360: Save Flags: Ccs(173)

    Section 5-28 Flag/Register Instructions 5-28-2 SAVE FLAGS: CCS(173) Ladder Symbol Variations j CCS(173) (173) Description When the execution condition is OFF, CCS(173) is not executed. When the ex- ecution condition is ON, CCS(173) records the current status of the Arithmetic Flags in the CPU for later retrieval by the CCL(172) instruction.

  • Page 361: Save Register: Regs(176)

    Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) 5-28-4 SAVE REGISTER: REGS(176) Ladder Symbol Operand Data Area (176) D: 1 destination word CIO, G, A, DM REGS Variations j REGS(176) Description When the execution condition is OFF, REGS(176) is not executed. When the ex- ecution condition is ON, REGS(176) copies the data from data registers DR0, DR1, and DR2 to D, D+1, and D+2, and copies the data from index registers IR0, IR1, and IR2 to D+3, D+4, and D+5.
  • Page 362 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) STEP DEFINE: STEP(008) Ladder Symbol Operand Data Area (008) B: Bit CIO, G, A STEP (008) STEP STEP START: SNXT(009) Ladder Symbol Operand Data Area (009) B: Bit CIO, G, A SNXT Description STEP(008) uses a control bit to define the beginning of a section of the program called a step.
  • Page 363 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Two simple steps are shown below. In this example, the 1st step would be ex- ecuted from the time that CIO 00000 goes ON until CIO 000001 goes ON. The 2nd step would be executed for the time the CIO 000001 goes ON until CIO 000002 goes ON.
  • Page 364 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Flags A50012: The Step Flag is turned ON for one cycle when STEP(008) is executed and if necessary it can be used to reset counters in steps as shown below. 0000 Address Instruction Operands (009) SNXT 001000...
  • Page 365 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) The following diagram demonstrates the flow of processing and the switches that are used for execution control. Process A Loading Process B Part Installation Process C Inspection/discharge The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(009) that starts the next step.

  • Page 366: Step Define And Step Start: Step(008)/Snxt(009)

    Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Example 2: The following process requires that a product is processed in one of two ways, Branching Execution depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used.
  • Page 367 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) The program for this process, shown below, starts with two SNXT(009) instruc- tions that start processes A and B. Because of the way CIO 000001 (SW A1) and CIO 000002 (SW B1) are programmed, only one of these will be executed with an ON execution condition to start either process A or process B.
  • Page 368 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) The following diagram demonstrates the flow of processing and the switches that are used for execution control. Here, process A and process C are started together. When process A finishes, process B starts; when process C finishes, process D starts.
  • Page 369 Section 5-29 STEP DEFINE and STEP START: STEP(008)/SNXT(009) When both process B and process D have finished (i.e., when SW5 and SW6 turn ON), processes B and D are reset together by the SNXT(009) at the end of the programming for process B. Although there is no SNXT(009) at the end of process D, the control bit for it is turned OFF by executing SNXT(009) 050004.

  • Page 370: Subroutines

    Section 5-30 Subroutines 5-30 Subroutines Subroutines break large control tasks into smaller ones and enable you to reuse a given set of instructions. When the main program calls a subroutine, control is transferred to the subroutine and the subroutine instructions are executed. The instructions within a subroutine are written in the same way as main program code.

  • Page 371: Subroutine Call: Sbs(151)

    Section 5-30 Subroutines Example When CIO 000000 is ON in the following example, the instructions between SBN(150) 001 and RET(152) are executed once before returning to execute the next instruction line after SBS(151). 0000 Address Instruction Operands (151) 00000 000000 00001 SBS(151) (Other instructions)
  • Page 372 Section 5-30 Subroutines the subroutine defined with SBN(150) 00). The following diagram illustrates two levels of nesting. SBN(150) 010 SBN(150) 011 SBN(150) 012 SBS(151) 010 SBS(151) 011 SBS(151) 012 RET(152) RET(152) RET(152) The following diagram illustrates program execution flow for various execution conditions for two SBS(151).

  • Page 373: Macro: Mcro(156)

    Section 5-30 Subroutines 5-30-3 MACRO: MCRO(156) Ladder Symbol Operand Data Areas (156) N: Subroutine number 000 to 999 or 000 to 099 MCRO N S: First input parameter word CIO, G, A, T, C, DM Variations D: First output parameter word CIO, G, A, T, C, DM ↑MCRO(156) Description...
  • Page 374 Section 5-30 Subroutines Main Program Subroutine Call CIO 0200 A200 CIO 0201 A201 CIO 0202 A202 CIO 0203 A203 Input (Processing) Output CIO 0300 A204 CIO 0301 A205 CIO 0302 A206 CIO 0303 A207 Return Program Examples The following examples show how MCRO(156) can be used to simplify a pro- gram.

  • Page 375: Stack Instructions

    Section 5-31 Stack Instructions Address Instruction Operands A50013 (156) MCRO 010 0000 0100 00000 A50013 00001 MCRO(156) (156) 0000 MCRO 010 0002 0105 0100 00002 MCRO(156) (156) MCRO 010 0005 0120 0002 0105 (156) 00003 MCRO(156) MCRO 010 0010 0150 0005 0120 00004...

  • Page 376: Push Onto Stack: Push(161)

    Section 5-31 Stack Instructions Example When CIO 000000 is ON in the following example, SSET(160) defines a 7-word stack from D00000 to D00006. The memory address of the last word in the stack, $2006, is written into D00000 and the memory address of TB1+2, $2002, is written into D00001.

  • Page 377: Last In First Out: Lifo(162)

    Section 5-31 Stack Instructions Example When CIO 000000 is ON in the following example, PUSH(161) is used to write the data in CIO 1000 to the 7-word stack from D00000 to D00006. The stack pointer contains the memory address of D00002, so the data in CIO 1000 is co- pied to D00002.

  • Page 378: First In First Out: Fifo(163)

    Section 5-31 Stack Instructions Memory Memory address address D00000 $2006 (Final stack address) $2000 D00000 $2006 (Final stack address) $2000 D00001 $2004 (Stack pointer) $2001 D00001 $2003 (Stack pointer) $2001 D00002 ABCD $2002 D00002 ABCD $2002 D00003 37B4 $2003 D00003 37B4 (Moved to CIO 0200) $2003 D00004 0000 $2004...

  • Page 379: Data Tracing

    Section 5-32 Data Tracing 5-32 Data Tracing Data tracing can be used to facilitate debugging programs and is described in detail in the SSS Operation Manuals. This section shows the ladder symbols for TRSM(170) and MARK(171) and provides example programs. 5-32-1 TRACE MEMORY SAMPLING: TRSM(170) Ladder Symbol (170)
  • Page 380 Section 5-32 Data Tracing Example The following shows the basic program and operation for data tracing. The Sam- pling Start Bit starts the sampling. The data is read and stored into trace memory. When the Trace Start Bit is received, the CPU looks at the delay and marks the trace memory accordingly.

  • Page 381: Mark Trace: Mark(174)

    Section 5-32 Data Tracing 5-32-2 MARK TRACE: MARK(174) Ladder Symbol Operand Data Area (174) N: Mark number MARK Description Like TRSM(170), MARK(174) is used in the program to mark locations where specified data is to be stored in Trace Memory. Two words may be designated for tracing, and each time the MARK(174) instruction is executed, the word ad- dress, content, and mark number are stored in Trace Memory.

  • Page 382: Special I/O Instructions

    Section 5-33 Special I/O Instructions 5-33 Special I/O Instructions The Special I/O Instructions are used to write data to or read data from Special I/O Units, such as an ASCII Unit. Refer to the operation manual of the Special I/O Unit for details on the use and content of data transfers.
  • Page 383 Section 5-33 Special I/O Instructions 4. No more than one READ(190) and/or WRIT(191) cannot be executed for the same Special I/O Unit at the same time. Be sure the first instruction has completed execution before starting execution another READ(190)/WRIT(191) instruction. Note Refer to page 101 for general precautions on operand data areas.

  • Page 384: I/O Read 2: Rd2(280)

    Section 5-33 Special I/O Instructions 5-33-2 I/O READ 2: RD2(280) Ladder Symbol Operand Data Areas (280) C: Control word CIO, G, A, T, C, #, DM, DR, IR S: Source word D: First destination word CIO, G, A, T, C, DM Description When the execution condition is OFF, RD2(280) is not executed.
  • Page 385 Section 5-33 Special I/O Instructions Example When CIO 000000 is ON in the following example, the contents of words 02 through 12 in the Special I/O Unit’s memory area are read in order, one word at a time, through CIO 0004, and the contents that are read are transferred in order to D00300 through D00311.

  • Page 386: I/O Write: Writ(191)

    Section 5-33 Special I/O Instructions 5-33-3 I/O WRITE: WRIT(191) Ladder Symbol Operand Data Areas (191) N: Words to transfer CIO, G, A, T, C, #, DM, DR, IR WRIT S: 1 source word CIO, G, A, T, C, DM Variations D: Destination word j WRIT(191) Description...
  • Page 387 Section 5-33 Special I/O Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): D is not allocated to a Special I/O Unit. N is not BCD. Instruction executed transferring more than 255 words to a Special I/O Unit on a SYSMAC BUS/2 Slave Rack.

  • Page 388: I/O Write 2: Wr2(281)

    Section 5-33 Special I/O Instructions Example 2 The following program section shows one way to pass data from a weighing sta- tion on a conveyor line through an ASCII Unit to a printer or other external de- vice. Data is input via CIO 0002, stored in D00001 through D00100, and output via CIO 0003.
  • Page 389 Section 5-33 Special I/O Instructions The words that are to be transferred are specified by the control word. The con- tents of the control word are as follows: Control Word Contents Number of words to be written (binary 00 to FF) Beginning address for writing (binary 00 to FF) The beginning address for writing specifies the rightmost (lowest) word of the range of in the Special I/O Unit into which the data is to be written.

  • Page 390: Network Instructions

    Section 5-34 Network Instructions PC Memory Special I/O Unit Memory D: Destination word Beginning address for writing Words allocated to Special I/O Unit Number of words to be written S: First source word 5-34 Network Instructions The Network Instructions are used for communicating with other control PCs or other Units linked through the SYSMAC NET Link System, SYSMAC LINK Sys- tem, or Controller Link System.

  • Page 391: Enable Access: Iors(188)

    Section 5-34 Network Instructions IOSP(187) is designed to temporarily disable access, e.g., during read/write op- erations. Servicing of CPU Bus Units, the host link interface, and Programming Devices can be disabled for longer intervals by turning ON the bits shown in the following table.
  • Page 392 Section 5-34 Network Instructions If the message data changes while the message is being displayed, the display will also change. If not all sixteen words are required for the message, it can be stopped at any point by inputting “OD.” When OD is encountered in a message, no more words will be read and the words that normally would be used for the message can be used for other purposes.

  • Page 393: Network Send: Send(192)

    Section 5-34 Network Instructions 5-34-4 NETWORK SEND: SEND(192) Ladder Symbol Operand Data Areas (192) S: 1 source word CIO, G, A, T, C, DM SEND D: 1 destination word CIO, G, A, T, C, DM Variations C: 1 control word CIO, G, A, T, C, DM j SEND(192) Description...
  • Page 394 Section 5-34 Network Instructions 3. Indicates a Unit as shown in the following table. Unit Setting SYSMAC NET Link, SYSMAC LINK, $10 to $1F: Unit numbers 0 to F or Controller Link Unit $FE: The local Unit SYSMAC BUS/2 Master, BASIC Unit, $10 to $1F: Unit numbers 0 to F or Personal Computer Unit SYSMAC BUS/2 Group-2 Slave...

  • Page 395: Network Receive: Recv(193)

    Section 5-34 Network Instructions Content of *DM word is not BCD when set for BCD. Flags ER (A50003): Example The following example is for transmission to a PC through a SYSMAC NET Link System. When CIO 000000 is ON, the SEND(192) transfers the content of CIO 0100 through CIO 0104 to D05001 through D05005 of the PC on node 3 of network 1.
  • Page 396 Section 5-34 Network Instructions Control Data SYSMAC NET Link Systems Set the source node number to $00 to send data within the PC executing the instruction. Refer to the SYSMAC NET Link System Manual for details. Word Bits 00 to 07 Bits 08 to 15 Number of words (1 to 0990 in 4-digit hexadecimal, i.e., $0001 to $03DE) Source network address...

  • Page 397: Deliver Command: Cmnd(194)

    Section 5-34 Network Instructions 2. Set the BASIC Unit interrupt number when a BASIC Unit is designated. 3. Same as for SYSMAC NET Link Systems. See note 3 above. 4. Values of $01 to $3E indicate nodes 1 to 62. Set to $00 to receive data from within the local PC.
  • Page 398 Section 5-34 Network Instructions If the destination node number is $FF, the command will be broadcast to all nodes in the designated network. Normally a response is required with CMND(194) and C+3 bit 15 is turned OFF. The response function is disabled when the command is sent to all nodes.
  • Page 399 Section 5-34 Network Instructions 4. Indicates a Unit as shown in the following table. Unit Setting SYSMAC NET Link, SYSMAC LINK, $10 to $1F: Unit numbers 0 to F or Controller Link Unit $FE: The local Unit SYSMAC BUS/2 Master, BASIC Unit, $10 to $1F: Unit numbers 0 to F or Personal Computer Unit SYSMAC BUS/2 Group 2 Slave...

  • Page 400: About Network Instruction Operations

    Section 5-34 Network Instructions Example This example shows CMND(194) used to transmit a command to the PC on node 3 of network 1 to change the PC to MONITOR mode when CIO 00000 is ON. D05001 is the first word to receive the response, and D04001 through D04003 contain the command data.
  • Page 401 Network Instructions is executed. Final processing for transmissions/receptions is performed during servicing of Link Units. The CVM1D PCs always operate in synchronous operation, so it isn’t necessary to take steps to synchronize data processing as in the CVM1 and CV-series PCs.
  • Page 402 Section 5-34 Network Instructions Port Enabled Flag 0000 A502 0128 (011) KEEP 012800 0128 0128 (030) jMOV CIO 000000 is turned ON to start transmission. CIO #000A D00000 012800 remains ON until SEND(192) has completed. (030) jMOV #0001 D00001 Data is placed into control data words to specify the 10 words to be transmitted to the PC of node 3 of network 01, through port 4, with response, 5 retries, (030)
  • Page 403 Section 5-34 Network Instructions Address Instruction Operands Address Instruction Operands 00020 A50204 00000 000000 00001 A50204 00021 AND NOT 012800 00002 AND NOT 012802 00022 012803 00003 012801 00023 KEEP(011) 012802 00024 012802 00004 KEEP(011) 012800 jMOV(030) 00005 012800 00025 jMOV(030) 00006 #000A...
  • Page 404 Section 5-34 Network Instructions Programming Example: The following program shows how to synchronize data transmission during Synchronizing Data asynchronous operation using IOSP(187) and IORS(188). In the program in PC A (the sending PC), the data is set in memory while the Enabled Flag is ON, i.e., when SEND(192) is not being executed, and a code is added in the last word of data to verify that the data has been transmitted suc- cessfully.

  • Page 405: Block Programming Instructions

    Section 5-35 Block Programming Instructions 5-35 Block Programming Instructions Block programming can be used to program operations that are difficult to pro- gram with ladder diagrams, such as certain data computations. Effective block programming can be use to reduce the number of programming steps required for certain operations, thus reducing the cycle time and increasing overall pro- cessing speed.

  • Page 406: Block Program Begin/End: Bprg(250) / Bend<001

    Section 5-35 Block Programming Instructions The following instructions cannot be used in block programs. Group Mnemonic Remarks Bit control DIFU(013) instructions DIFD(014) KEEP(011) Use SET(016) and RSET(017). (There are not block SET and RSET instructions for not block SET and RSET instructions for OUT NOT CV-series PCs.) Interlock and...

  • Page 407: Branching-If<002>, Else<003>, And Iend<004

    Section 5-35 Block Programming Instructions Block programs cannot be nested. Example When CIO 000000 is ON in the following diagram, the block program between program addresses 000501 and 000600 will be executed. 0000 (250) Address Instruction Operands BPRG 000500 BPRG(250) Block program Block program.
  • Page 408 Section 5-35 Block Programming Instructions IF<002> NOT with an IF<002> NOT to ELSE to IEND Operand IF<002> NOT B When B is OFF, C is executed. ELSE<003> When B is ON, D is executed. IEND<004> IF<002> without an IF<002> to ELSE to IEND Operand LD 00000 AND 00001...
  • Page 409 Section 5-35 Block Programming Instructions The second block is executed when CIO 000002 is ON and shows nesting two levels. If CIO 000003 and CIO 000004 are both ON, the contents of CIO 1200 and CIO 0002 are added and the result is placed in D00010 and then 0001 is moved into D00011 based on the status of CY.

  • Page 410: One Cycle And Wait: Wait<005

    Section 5-35 Block Programming Instructions 5-35-4 ONE CYCLE AND WAIT: WAIT<005> Ladder Symbol Operand Data Area B: Bit CIO, G, A, T, C WAIT<005> WAIT<005> WAIT<005> NOT Description WAIT<005> and WAIT<005> NOT allow you to inhibit execution of the por- tion of block program from WAIT<005>...

  • Page 411: Conditional Block Exit: Exit<006

    Section 5-35 Block Programming Instructions The execution flow for this example would be as shown below: 000000 000001 Initial execution 000000 000001 OFF The following example would work similarly, except that execution of WAIT<005> would be based on an AND between the status of CIO 000001 and CIO 000002.

  • Page 412: Loop Control-Loop<009>/Lend<010

    Section 5-35 Block Programming Instructions When using EXIT<006> without an bit operand, the instructions used to create the execution condition for EXIT<006> must begin with LD. Execution Flow Examples When CIO 000000 is OFF, the block program is executed as normal. If CIO 000001 turns ON, however, A is executed and then B is skipped and program control jumps to BEND<001>.

  • Page 413: Block Program Pause/Restart : Bpps<011>/Bprs<012

    Section 5-35 Block Programming Instructions IEND<004> IEND<004> IEND<004> LEND<010> LEND<010> • Loops cannot be nested within loops. Incorrect: LOOP<009> LOOP<009> LEND<010> LEND<010> • Do not reverse the order of LOOP and LEND. Incorrect: LEND<010> LOOP<009> Execution Flow Examples When CIO 000000 is ON, the block program is executed. After A is executed, B and the IORF(184) after it will be executed repeatedly until CIO 000001 is ON, at which time C will be executed and the block program will end.

  • Page 414: High-Speed Timer/Timer Wait: Timw<013>/Tmhw<015

    Section 5-35 Block Programming Instructions Example If CIO 000000 is ON, the following program suspends execution of either block program 01 or block program 02 depending on the status of CIO 000001. The block program that was suspended is then restarted after 10 seconds.

  • Page 415: Counter Wait: Cntw<014

    Section 5-35 Block Programming Instructions Example In the following example, B will be executed 20 seconds after A whenever CIO 000000 is ON, and CIO 002000 will be set 0.2 seconds after CIO 000001 goes ON. 0000 (250) Address Instruction Operands BPRG 000000...
  • Page 416 Section 5-35 Block Programming Instructions Example In the following example, B will be executed after the execution of A and after 7,000 counts of CIO 000100 while CIO 000000 is ON. 0000 (250) Address Instruction Operands BPRG 000000 000000 000001 BPRG(250) CNTW<014>...

  • Page 417: Program Execution Timing

    SECTION 6 Program Execution Timing This section explains the execution cycle of the PC and shows how to calculate the cycle time and I/O response times. I/O response times in Link Systems are described in the individual System Manuals. PC Operation .

  • Page 418: Pc Operation

    Section 6-1 PC Operation PC Operation This section details basic CPU operation of CVM1D PCs. 6-1-1 Initialization The following diagram shows initialization in a duplex CVM1D PC on power-up: Active (ACT) CPU Unit Standby (STB) CPU Unit Power application Power application...

  • Page 419: Synchronous Operation In The Duplex System

    6-1-2 Synchronous Operation in the Duplex System The active CPU and standby CPU perform synchronous processing as shown in the following diagram. The CVM1D PCs always operate in synchro- nous operation, asynchronous operation cannot be set in the PC Setup.

  • Page 420: I/O Refreshing Limitations

    Section 6-1 PC Operation 6-1-3 I/O Refreshing Limitations In CVM1D PCs, cyclic refreshing is the only method used to refresh the entire I/O area. The I/O REFRESH instruction (IORF(184)) can be used to refresh specific ranges of I/O words. • The refreshing method cannot be changed to “scheduled refreshing” or “zero- cross refreshing”...

  • Page 421: I/O Refreshing In Sysmac Bus/2 And Sysmac Bus Systems

    Section 6-1 PC Operation 6-1-6 I/O Refreshing in SYSMAC BUS/2 and SYSMAC BUS Systems SYSMAC BUS/2 I/O refreshing takes place once each PC cycle, but I/O points in the SYSMAC BUS/2 System may not be refreshed every cycle if the SYSMAC BUS/2 commu- nications cycle is longer than the PC cycle.

  • Page 422: Cycle Time

    Section 6-2 Cycle Time 2. The CPU will begin initialization when the CPU reset signal is turned OFF. 3. When CPU initialization is completed, the program will be executed. The new power interruption time is written to A012 and A013 and the new num- ber of power interruptions is written to A014.

  • Page 423: Synchronous Operation

    Cycle Time 6-2-1 Synchronous Operation CVM1D PCs always operate in synchronous operation; the instruction execu- tion processing and Programming Device servicing are synchronized in a single cycle. The cycle time is thus the sum of the time required for instruc-...

  • Page 424: Duplex Initialization

    Section 6-2 Cycle Time Do not leave Service Disable Bits ON for longer than is necessary; service be- tween the PC and the designated Unit will be stopped completely as long as the corresponding Service Disable Bit is ON. Word(s) Bit(s) Function A015...

  • Page 425: Switching From Duplex To Simplex Operation

    Section 6-2 Cycle Time The configuration of the PC can greatly affect the cycle time. The following table shows how duplex initialization will increase the cycle time for a PC configuration with a normal cycle time of 20 ms. Number of EM banks Program size Maximum cycle time Minimum...

  • Page 426: Example Of Error Detection Program

    PC. 2. In the CVM1D, PC operation is stopped for the times shown in the following table but there is no effect on cycle time (i.e., those times are not added to...

  • Page 427: Potential Problems With Event Processing

    Section 6-3 Calculating Cycle Time Online edit operation Stopped time Instruction block inserted or deleted at the beginning of 1 Approx. 0.5 s 62K-word program. Instruction block including JME(005) deleted at the beginning Approx. 2.0 s of a 62K-word program. While PC operation is stopped, output status is retained and inputs are not accepted and communications with SYSMAC NET, SYSMAC LINK, SYS- MAC BUS/2, Host Link, and Programming Devices are stopped.
  • Page 428 This section shows a basic example of cycle time calculation. Operating times are given in the tables in 6-2 Cycle Time. Here, we’ll compute the cycle time for a CVM1D controlling only I/O Units, five on the CPU Rack and ten on an Expansion I/O Rack. The PC configura- tion for this is shown below.

  • Page 429: Instruction Execution Times

    Instruction Execution Times Instruction Execution Times This following table lists the execution times for CVM1D instructions. The maxi- mum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it im- plies the content of any word except for indirectly addressed DM words.
  • Page 430 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( Constant for SV 3.32 R or IL: 7.8 *DM for SV R or IL: 10.8 1.25 Constant for SV R or IL: 1.25 *DM for SV R: 5.75 IL: 1.25...
  • Page 431 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CPS(026) Comparing constants and words Comparing two *DM 6.25 !CPS(026) Amount added per input word at time of +5.0 comparison Amount added per output word at time of +4.0 comparison Other areas at time of comparison...
  • Page 432 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( Constant → (word + word) DIST(044) 1.13 *DM → (*DM + *DM) (word + word) → word COLL(045) (*DM + *DM) → *DM BXFR(046) Transferring 1 word from word to word 16.1...
  • Page 433 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( RORL(067) When rotating two words to clockwise 0.88 When rotating two *DM to clockwise SLD(068) When shifting 1 word 11.4 When shifting 1000 DM words using *DM SRD(069) When shifting 1 word 11.4...
  • Page 434 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( INCL(094) Word increment 12.9 0.88 *DM increment 13.9 DECL(095) Word decrement 12.8 *DM decrement 13.8 INBL(096) Word increment *DM increment DCBL(097) Word decrement *DM decrement BIN(100) When converting a word to a word...
  • Page 435 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( Constant OR word → word ORW(131) 1.13 *DM OR *DM → *DM Constant XOR word → word XORW(132) *DM XOR *DM → *DM Constant XNOR word →...
  • Page 436 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( SUM(167) When adding 1 word 1.13 When adding 1000 words via *DM 144 ms TRSM(170) When sampling 1 point + 0 word 18.0 When sampling 12 points + 3 words 42.0...
  • Page 437 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( RLNC(260) Rotating word 9.63 0.88 Rotating *DM 11.8 RRNC(261) Rotating word 9.75 Rotating *DM 11.9 RLNL(262) Rotating word 10.8 Rotating *DM 12.9 RLNL(263) Rotating word 10.8...
  • Page 438 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( <(310) Comparing constant and word 12.3 5.13 Comparing *DM and *DM 16.8 <L(311) Comparing constant and word 13.0 Comparing *DM and *DM 17.5 <S(312) Comparing constant and word...
  • Page 439 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( Constant + word → word +BC(406) 7.50 1.13 *DM + *DM → *DM 11.5 Constant + word → word +BCL(407) 17.9 *DM + *DM → *DM 21.8 Constant –...
  • Page 440 Section 6-4 Instruction Execution Times µ µ Instruction Words Conditions ON execution time ( OFF execution time ( Word → word FLT(452) *DM → *DM Word → word FLTL(453) *DM → *DM Constant + word → word 1.13 +F(454) *DM + *DM → *DM Constant –...

  • Page 441: I/O Response Time

    Section 6-5 I/O Response Time I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the input re- fresh period.

  • Page 442: I/O Response Times In A Sysmac Bus System

    Section 6-5 I/O Response Time Maximum I/O Response The PC takes longest to respond when it receives the input signal just after the Time input refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time.

  • Page 443: I/O Response Times In A Sysmac Bus/2 System

    Section 6-5 I/O Response Time Minimum I/O Response The PC responds most quickly when the Master receives the input signal just Time prior to I/O refreshing. This situation is illustrated below. Cycle time Program execution Cycle Programming Device servicing I/O refresh Buffer in Master Transmission time Input signal...
  • Page 444 Section 6-5 I/O Response Time The data in the following table is used to produce the minimum and maximum cycle times shown calculated below. Input ON delay 1.5 ms Cycle time 20 ms Output ON delay 15 ms Communications cycle time 5 ms (one group 3, 58M Slave) Minimum I/O Response The PC responds most quickly when it receives an input signal just prior to SYS-...

  • Page 445: Pc Setup

    The PC Setup can be changed from the SSS. Refer to SSS Operation Manuals for details changing settings. The use of each parameter in the PC Setup is described where relevant in this manual and in other CVM1D manuals.

  • Page 446: Pc Setup Overview

    To prevent I/O status from being cleared when power is turned off and on. when power is turned on. D:Power on flag Fixed at “Do not hold” in CVM1D PCs. (A00011) C:Startup mode Specifies the initial PC operating mode. To automatically start the PC when power is turned ON.

  • Page 447: Pc Setup Details

    Changes to this setting are effective the next time the power is turned ON. (Default: A00012 turned OFF) Restart Continuation This setting is fixed at “Do not hold” (A00011 turned OFF) in CVM1D PCs. Bit status (A00011) (Power on flag) C:Startup mode Designate the PC operating mode to be set when PC power is turned ON.
  • Page 448 SSS, but the setting is ignored in CVM1D operation.) I/O interrupts Not applicable in CVM1D PCs. Power OFF interrupt This setting is fixed at “No power OFF interrupt” in CVM1D PCs. Dup action process SFC instructions are not used in CVM1D PCs. Step timer SFC instructions are not used in CVM1D PCs.
  • Page 449 O:CV-SIOU 1st addr Not used. P:Power break This setting is fixed at 0 ms (no momentary power interruptions) in CVM1D PCs. Q:Cycle time Set the minimum cycle time to between 0 and 32,000 ms. If the actual cycle time is less than the set cycle time, execution will be halted until the set cycle time elapses before the next cycle is executed.

  • Page 450: Pc Setup Default Settings

    G:Execute C:Execute process Synchronous (Fixed) control 2 (This setting is changed to “asynchronous” when the PC Setup is initialized with SSS, but the setting is ignored in CVM1D operation.) I:I/O interrupt Nesting D:Power OFF interrupt Disable (Fixed) A:Dup action process...
  • Page 451 Section 7-3 PC Setup Default Settings Parameter Default value L:Group 1,2 1st addr (First words for SYSMAC BUS/2 Slaves) Group 1: CIO 0200 CIO 0400 CIO 0600 CIO 0800 Group 2: CIO 0250 CIO 0450 CIO 0650 CIO 0850 M:Trans I/O addr (First words for I/O Terminals) CIO 2300 CIO2332 CIO 2364 CIO2396 CIO 2428 CIO 2460 CIO 2492 CIO 2524...

  • Page 452: Index

    Index adding to clock time, 339 compensation, 341 setting, 9 acronym, definition, 27 subtracting from clock time, 340 address tracing. See tracing clock pulse bits, 58 addresses commands, delivering commands through a network, 392 data area, description, 27 compatible devices, 7 memory, description, 27 complements, calculating, 336 addressing, indirect.
  • Page 453 Index See also Units DEBUG mode, description, 6 definition, 38 decimal points, 29 disabling service, 48, 420 decrementing, 301–305 Duplication Error Flags, 53 Error Flags, 53, 55 definers, definition, 100 I/O allocation, 38 differentiated instructions, 103 Initializing Flags, 50 function codes, 100 Initializing Wait Flag, 50 service interval, 51 digit numbers, 28...
  • Page 454 Index exponents, 299 I/O Setting Error Flag, 53 I/O Verification Error Flag, 56 Extended PC Setup, definition, 19 I/O Verification Error Wait Flag, 50 Indirect DM BCD Error Flag, 56 Instruction Execution Error, 57 Jump Error Flag, 56 LE, 57 Memory Card flags, 51 failure point detection, 344 Memory Card Format Error Flag, 51...
  • Page 455 Index I/O allocations combining with OR, 71 displaying the first I/O word on a Rack, 22 AND LD, 72, 111 example, 34 combining with OR LD, 75 using in logic blocks, 73 I/O Area, 32–36 AND NOT, 70, 107 I/O bits ANDL(134), 333 definition, 32 ANDW(130), 330...
  • Page 456 Index using in interlocks, 121 MOVB(042), 187 using in jumps, 123 MOVD(043), 189 DIST(044), 190 MOVL(032), 177 MOVQ(037), 182 DIV(073), 242 MOVR(036), 181 DIVL(077), 246 MSG(195), 386 DMPX(111), 216 MTIM(122), 138 DOWN(019), 109 MUL(072), 241 DVB(083), 253 MULL(076), 245 DVBL(087), 257 MVN(031), 176 ELSE<003>, 402 MVNL(033), 178...
  • Page 457 Index SQRT(466), 298 Interrupt Input Units, 416 SRCH(164), 353 IR. See Index Registers SRD(069), 174 SSET(160), 370 STC(078), 238 J–L STEP(008), 356 SUB(071), 239 jump numbers, 123 SUBL(075), 244 SUM(167), 309 jumps, 122–125 TAN(462), 294 CJP(221) and CJPN(222), 125 TCMP(023), 198 ladder diagrams testing bit status, 110 See also programming...
  • Page 458 Index floating-point addition, 286 output signal, definition, 3 floating-point data, 280 OV. See flags, overflow floating-point division, 289, 313 floating-point multiplication, 288 floating-point subtraction, 287 linear extrapolation, 316 logarithm, 300 parameters, PC Setup, 442 square root, 298, 310, 312 See also PC Setup maximum cycle time, extending, 349 memory areas, definition, 27 definition, 3...
  • Page 459 Index servicing, in asynchronous operation, 419 switching, from duplex to simplex operation, 421 synchronous operation, 415, 419 programs capacity, 9 SYSMAC BUS Remote I/O System execution, 90 disabling read/write access, 385 disabling refreshing, 48, 420 Protect Keyswitch, 13 enabling read/write access, 386 PV, timers and counters, 127 Error Flags and Check Bits, 54 I/O allocation, 38...
  • Page 460 Index use in branching, 80 I/O Interface Units. See display I/O Units, definition, 3 tracing, 374–375 Interrupt Input Units, 416 effect of instruction trace on cycle time, 422 Link Units, definition, 4 flags and control bits, 374, 376 Power Supply Unit, 52 trigonometric functions Special I/O Units converting to angles, 295, 296, 297...

  • Page 461: Revision History

    Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W351-E1-2 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
  • Page 462 SYSMAC CVM1D Duplex System Programmable Controllers Operation Manual Revised August 2001...
  • Page 464 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.
  • Page 466 ........... . CVM1D Program Memory .
  • Page 467 TABLE OF CONTENTS SECTION 5 Instruction Set ........Notation .
  • Page 468 Section 5 explains each instruction in the CVM1D PC instruction set and provides the ladder diagram symbols, data areas, and flags used with each.

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