Figure 9. Bypass_Reg Supervisor Reset Connection - ST STM32F74 Series Getting Started

AN4661
•
In regulator OFF mode, the following features are no more supported:
–
–
–
–
1. V
CAP2
V
CAP1
The following conditions must be respected:
•
V
DD
domains.
•
If the time for V
reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
V12 minimum value and until V
•
Otherwise, if the time for V
V
DD
• If V
CAP
be asserted low externally.
logic power domain (V
PA0 pin should be used for this purpose, and act as power-on reset on V12 power
domain.
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic
power domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on
reset. As a consequence, PA0 and NRST pins must be managed separately if the
debug connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.

Figure 9. BYPASS_REG supervisor reset connection

is not available on all packages. In that case, a single 100 nF decoupling capacitor is connected to
should always be higher than V
to reach V12 minimum value is smaller than the time for V
CAP
to reach 1.7 V, then PA0 could be asserted low externally.
goes below V12 minimum value and V
).
CAP
to avoid current injection between power
CAP
reaches 1.7 V.
DD
to reach V12 minimum value is smaller than the time for
CAP
DD
DocID027559 Rev 2
Power supplies
is higher than 1.7 V, then PA0 must
to
DD
reaches
CAP
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