Flexible Memory Controller (Fmc) Interface - ST STM32F74 Series Getting Started

AN4661 Recommended PCB routing guidelines for STM32F745xx/STM32F756xx devices
Interface signal layout guidelines:
•
Reference the plane using GND or PWR (if PWR, add 10nf switching cap between
PWR and GND)
•
Trace the impedance: 50Ω ± 10%
•
The skew being introduced into the clock system by unequal trace lengths and loads,
minimize the board skew, keep the trace lengths equal between the data and clock.
•
The maximum skew between data and clock should be below 250 ps @ 10mm
• The maximum trace length should be below 120mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
•
The trace capacitance should not exceed 20 pF at 3.3V and 15pF at 1.8V
•
The maximum signal trace inductance should be less than 16nH
•
Use the recommended pull-up resistance for CMD and data signals to prevent bus
floating.
•
The mismatch within data bus, data and CK or CK and CMD should be below 10mm.
•
Keep the same number of vias between the data signals
Note: The total capacitance of the SD memory card bus is the sum of the bus master capacitance
C , the bus capacitance C
HOST
to this line. The total bus capacitance is C
STM32F74xxx/STM32F75xxx, bus is all the signals and Card is SD card.
8.4.2

Flexible memory controller (FMC) interface

Interface connectivity
The FMC controller and in particular SDRAM memory controller which has many signals,
most of them have a similar functionality and work together. The controller I/O signals could
be splitted in four groups as follow:
• An address group which consists of row/column address and bank address
•
A command group which includes the row address strobe (NRAS), the column address
strobe (NCAS), and the write enable (SDWE)
•
A control group which includes a chip select bank1 and bank2 (SDNE0/1), a clock
enable bank1 and bank2 (SDCKE0/1), and an output byte mask for the write access
(DQM).
• A data group/lane which contains 8 signals
(DQM).
a.It depends of the used memory: SDRAM with x8 bus widths have only one data group,
while x16 and x32 bus-width SDRAM have two and four lanes, respectively.
itself and the capacitance C
BUS
= C + C
L Host
(a)
: the eight D (D7–D0) and the data mask
DocID027559 Rev 2
of each card connected
CARD
+ N*C where Host is
Bus Card
37/45
44