Pcie-Frm24_C Board Function; Block Diagram - DAQ system PCIe-FRM24 C User Manual

2. PCIe-FRM24_C Board Function

2-1 Block Diagram

As shown in the figure below, in the case of PCIe-FRM24_C, FPGA Core Logic is in charge of
overall control. Main functions include Frame Data reception, UART data transmission/reception
for this, Camera Control signal and external trigger.
These functions are performed using API in PC through PCI Express GEN2 4x interface.
PCI Express
4x BUS
MEM Decoder
The FPGA core logic is programmed using JTAG, and the logic program is saved in FPGA
Program Logic and loaded when power is applied.
PCIe-FRM24_C INTERNAL BLOCK - FPGA
PCI Target
/ Master
To each IO
Module
IO Decoder
DPRAM
CLOCK syn.
Interrupt
Controller
(0xb0)
INT sources in Chip
From Ext.
[Figure 2-1. PCIe-FRM24_C Block Diagram]
Local Bus
Address
Data(Mem,I/O)
BUS Mux
Interrupt controller
Camera Link(LVDS)
Ext. Address, Data, Control
PCIE-FRM24_C User's Manual
Reserved
(0x00 – 0x5F)
UART
(0x60)
Reserved
(0x70 – 0xAF)
(0xC0)
DIO
(0xD0)
Reserved
(0xE0 – 0xFF)
MEM Decoder
Local BUS
5