Camera Link & Pcie-Frm24_C - DAQ system PCIe-FRM24 C User Manual

2-4 Camera Link & PCIe-FRM24_C
PCIe-FRM24_C supports Camera Link Base/Medium/Full Configuration. Base Configuration
consists of 4 LVDS signal lines serializing 28-bit parallel signals including 24 data bits and 4 enable
signals Frame Valid, Line Valid, Data Valid, and a spare, and 1 LVDS signal line for synchronizing
with the camera. , Asynchronous serial communication including 4 CC (Camera Control) signals
and 2 LVDS lines for communicating with the camera transmits a total of 11 LVDS signal lines
through one MDR cable. To use Medium/Full Configuration, another MDR cable is used and it has
a total of 64bit wide video path.
The transmitted signal is parallelized (Frame Valid, Line Valid, Data Valid, and a spare) of 12
video LVDS serial signals into 64-bit parallel video signals and control signals for each
specification (Frame Valid, Line Valid, Data Valid, and a spare) through the Channel Link chip in
PCIe-FRM24_C Deserilize). Also, one LVDS to synchronize the signal between the camera and PCIe-
FRM24_C makes a clock signal, and the remaining cameras control signals and communication
signals are converted into general TTL signal levels and used.
The figure shows the Camera Control output circuit that can send the control signal from the
PCIe-FRM24_C board to the Camera through the Camera-link cable. A total of 4 digital outputs
are output through the differential method. Each output is mapped to a digital output and
becomes an output. Each bit position is shown in [Figure 2-7] below.
Camera Control
CC_D0
CC_D1
CC_D2
CC_D3
[Figure 2-7. Camera Control LVDS Digital Output Circuit]
PCIE-FRM24_C User's Manual
CCx+
CCx-
CC1+
CC1-
CC2+
CC2-
CC3+
CC3-
CC4+
CC4-
10