Marvell 88E3015 Manual page 83

Table 53: PHY Specific Control Register II
Register 28
B i ts F i e l d
15:12 Reserved
11:10 MAC Interface
Mode
9:5 Reserved
4 EnLineLpbk
3 SoftwareMedia
Select
2 TDRWaitTime
1 EnRXCLK
0 SelClsA
Copyright © 2008 Marvell
January 4, 2008, Advance
M o d e H W S W
R s t R s t
R/W 0x0 Retain
R/W See Update
Desc.
R/W 0x00 Update
R/W 0x0 Retain
R/W See Update
Desc.
R/W 0x0 Retain
R/W 0x1 Update
R/W 0x0 Update
Document Classification: Proprietary Information
D e s c r i p t io n
Must be 0000
During Hardware Reset register 28.11:10 defaults as fol-
lows
MODE[2:0] 28.11:10
000 00
001 01
010 00
011 10
100 10
110 11
111 01
00 = RGMII where receive clock transition when
data transitions
01 = RGMII where receive clock transition when
data stable
10 = Non-Source Synchronous MII
11 = Source Synchronous MII
Set to 00000
0 = Disable Line Loopback
1 = Enable Line Loopback
During Hardware Reset register 28.3 defaults as follows
MODE[2:0] 28.3
000 0
001 0
010 1
011 0
100 1
110 0
111 1
0 = Select Copper Media
1 = Select Fiber Media
0 = Wait time is 1.5s before TDR test is started
1 = Wait time is 25 ms before TDR test is started
0 = Disable MAC interface clock (RXCLK) in sleep mode
1 = Enable MAC interface clock (RXCLK) in sleep mode
0 = Select Class B driver (typically used in CAT 5 appli-
cations)
1 = Select Class A driver - available for 100BASE-TX
mode only (typically used in Backplane or direct
connect applications, but may be used with CAT 5
applications)
Doc. No. MV-S103657-00, Rev. D
Register Description
Page 83