Marvell 88E3015 Manual page 13

Table 3: MII Interface
88E30 15 88E3 018
52 60
54 62
53 61
51 59
50 58
55 63
45 53
47 55
46 54
43 51
42 50
41 49
17 19
Copyright © 2008 Marvell
January 4, 2008, Advance
Pin Name Type
TX_CLK I/O, Z
TXD[3] I
TXD[2]
TXD[1]
TXD[0]
TX_CTRL/TX_EN
RX_CLK O, Z
RXD[3] O, Z
RXD[2]
RXD[1]
RXD[0]
RX_CTRL/RX_DV
RX_ER I/O, Z
Document Classification: Proprietary Information
De scrip tio n
MII Transmit Clock. TX_CLK provides a 25 MHz
and 2.5 MHz clock reference for TX_CTRL,
TX_ER, and TXD[3:0], depending on the speed.
TX_CLK is an output when in normal MII mode,
and is an input in source synchronous MII mode.
MII Transmit Data. TXD[3:0] presents the data nib-
ble to be transmitted onto the cable.
TXD[3:0] is synchronous to TX_CLK.
MII Transmit Enable. In MII mode, TX_CTRL is
used as TX_EN. When TX_CTRL is asserted, data
on TXD[3:0] along with TX_ER is encoded and
transmitted onto the cable.
TX_EN is synchronous to TX_CLK.
MII Receive Clock. RX_CLK provides a 25 MHz
and 2.5 MHz clock reference for RX_CTRL,
RX_ER, and RXD[3:0] depending on the speed.
MII Receive Data. Symbols received on the cable
are decoded and presented on RXD[3:0].
RXD[3:0] is synchronous to RX_CLK.
MII Receive Data Valid. Data received on the cable
is decoded and presented on RXD[3:0] and
RX_ER. In MII mode, RX_CTRL is used as
RX_DV.
RX_CTRL is synchronous to RX_CLK.
MII Receive Error. When RX_ER and RX_CTRL
are both asserted, the signals indicate an error
symbol is detected on the cable.
When RX_ER is asserted with RX_CTRL de-
asserted, a false carrier is detected on the cable.
RX_ER is synchronous to RX_CLK.
Doc. No. MV-S103657-00, Rev. D
Signal Description
Pin Description
Page 13