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Write to register 30 = b'000P PPPP 010N NNNN -- adjusts NMOS strength
Where PPPPP is the 5 bit value for the PMOS strength.
Where NNNNN is the 5 bit value for the NMOS strength.
The value of PPPPP or NNNNN will depend on your board. The '11111' value enables all fingers for maximum
drive strength, for minimum impedance. The '00000' value turns all fingers off for minimum drive strength, for max-
imum impedance. Use a scope to monitor the RX_CLK pin close to the destination. Start with the default auto-cal-
ibrated value and move in each direction to see how it affects signal integrity on your board.
Example: The automatic calibration has a 49 ohm target, but if the MII trace impedance on board was 60 ohms,
you see reflections from a scope capture taken at the destination. See
see that the reflections are eliminated in
Figure 12
and
Figure 13
display the trend lines for 1.8V and 2.5V PMOS and NMOS impedance settings.
NOTE: The trend lines displayed in
Figure 12: PMOS Output Impedance (1.8V, 2.5V) Trend Lines (TBD)
90
80
70
60
50
40
30
20
10
0
1
2 3
4
5 6 7
Copyright © 2008 Marvell
January 4, 2008, Advance
Figure
15.
Figure 12
and
Figure 13
2.5V
3.3V
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PMOS Register Value (Decimal)
Document Classification: Proprietary Information
Automatic and Manual Impedance Calibration
Figure
14. After manual calibration, you
use nominal values and may vary in production.
Doc. No. MV-S103657-00, Rev. D
Functional Description
Page 49
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