Marvell 88E3015 Manual page 72

88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 43: PHY Specific Status Register
Register 17
B i ts F i el d
15 Reserved
14 ResSpeed
13 ResDuplex
12 RcvPage
11 Resolved
10 RTLink
9:7 Reserved
6 MDI/MDIX
5 Reserved
4 Sleep
Doc. No. MV-S103657-00, Rev. D
Page 72
M o d e H W S W
R s t R s t
RO 0x0 0x0
RO 0x1 Retain
RO 0x1 Retain
RO, LH 0x0 0x0
RO 0x0 0x0
RO 0x0 0x0
RES Always Always
000 000
RO 0x0 0x0
RES Always Always
0 0
RO 0x0 0x0
Document Classification: Proprietary Information
D e s c r i p t io n
0
Resolved Speed
The values are updated after the completion of Auto-
Negotiation. The registers retain their values during soft-
ware reset. This bit is valid only after the resolved bit 11
is set.
0 = 10 Mbps
1 = 100 Mbps.
Resolved Duplex Mode
The values are updated after the completion of Auto-
Negotiation. The registers retain their values during soft-
ware reset. This bit is valid only after the resolved bit 11
is set.
0 = Half-duplex
1 = Full-duplex
Page Receive Mode
0 = Page not received
1 = Page received
Speed and Duplex Resolved. Speed and duplex bits (14
and 13) are valid only after the Resolved bit is set. The
Resolved bit is set when Auto-Negotiation has resolved
the highest common capabilities or Auto-Negotiation is
disabled.
0 = Not resolved
1 = Resolved
Link (real time)
0 = Link down
1 = Link up
Always 000.
MDI/MDIX Crossover Status
0 = Transmit on pins TXP/TXN, Receive on pins RXP/
RXN
1 = Transmit on pins RXP/RXN, Receive on pins TXP/
TXN
Always 0.
Energy Detect Status
0 = Chip is not in sleep mode (Active)
1 = Chip is in sleep mode (No wire activity)
Copyright © 2008 Marvell
January 4, 2008, Advance