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88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 2:
RGMII Interface
8 8E301 5
88E30 18
52
60
55
63
54
62
53
61
51
59
50
58
45
53
41
49
47
55
46
54
43
51
42
50
Doc. No. MV-S103657-00, Rev. D
Page 12
Pin Name
Typ e
TX_CLK/TXC
I
TX_CTRL/TX_CTL
I
TXD[3]/TD[3]
I
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
RX_CLK/RXC
O
RX_CTRL/
O
RX_CTL
RXD[3]/RD[3]
O
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
Document Classification: Proprietary Information
De scr ip tio n
RGMII Transmit Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
depending on speed. In RGMII mode, TX_CLK is
used as TXC.
RGMII Transmit Control. TX_EN is presented on
the rising edge of TX_CLK. In RGMII mode,
TX_CTRL is used as TX_CTL.
A logical derivative of TX_EN and TX_ER is pre-
sented on the falling edge of TX_CLK.
RGMII Transmit Data. In RGMII mode, TXD[3:0]
are used as TD[3:0].
The transmit data nibble is presented on TXD[3:0]
on the rising edge of TX_CLK.
RGMII Receive Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
derived from the received data stream depending
on speed. In RGMII mode, RX_CLK is used as
RXC.
RGMII Receive Control. RX_DV is presented on
the rising edge of RX_CLK. In RGMII mode,
RX_CTRL is used as RX_CTL.
A logical derivative of RX_DV and RX_ER is pre-
sented on the falling edge of RX_CLK.
RGMII Receive Data. In RGMII mode, RXD[3:0]
are used as RD[3:0].
The receive data nibble is presented on RXD[3:0]
on the rising edge of RX_CLK.
Copyright © 2008 Marvell
January 4, 2008, Advance
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