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Marvell 88E3016 Manual

Integrated 10/100 fast ethernet transceiver
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88E3016
Integrated 10/100 Fast Ethernet Transceiver
Marvell.
Moving Forward Faster
Doc. No. MV-S103164-00, Rev. A
January 4, 2008
Document Classification: Proprietary Information

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Summary of Contents for Marvell 88E3016

  • Page 1 88E3016 Integrated 10/100 Fast Ethernet Transceiver Doc. No. MV-S103164-00, Rev. A January 4, 2008 Document Classification: Proprietary Information Marvell. Moving Forward Faster...
  • Page 2 No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose.
  • Page 3 150 ppm clock frequency difference Media Independent Interface (RGMII). ± • IEEE 802.3u Auto-Negotiation support for auto- The 88E3016 device features a mode of operation matic speed and duplex selection supporting IEEE compliant 100BASE-FX fiber-optic • Far-End Fault Indication (FEFI) support for networks.
  • Page 4 Canceller XTAL_OUT Clock/ LED[2:0] LED/ RESETn Reset Configuration CONFIG[3:0] COMAn 2.5V CTRL25 Regulator 1.2V DIS_REG12 Regulator 88E3016 Device Functional Block Diagram Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 4 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 5: Table Of Contents

    88E3016 Device 64-Pin QFN Pinout ................8 Pin Description....................... 9 1.2.1 Pin Type Definitions ......................9 1.2.2 88E3016 64-Pin QFN Assignments - Alphabetical by Signal Name ........ 16 ............17 ECTION UNCTIONAL ESCRIPTION Reduced Gigabit Media Independent Interface (RGMII) ........... 18 Serial Management Interface ..................
  • Page 6 LECTRICAL PECIFICATIONS 4.1. Absolute Maximum Ratings ..................78 4.2. Recommended Operating Conditions ................79 Package Thermal Information ..................80 4.3.1 88E3016 Device 64-Pin QFN package................80 Current Consumption ....................81 4.4.1 Current Consumption AVDD + Center Tap ..............81 4.4.2 Current Consumption AVDDC..................81 4.4.3...
  • Page 7 FX Interface to 3.3V Fiber Transceiver............... 99 Transmitter - Receiver Diagram................100 88E3016 to 88E3016 Backplane Connection - 100BASE-FX Interface ....101 88E3016 to Another Vendor’s PHY - 100BASE-FX Interface through a Backplane102 Marvell® PHY to Marvell PHY Direct Connection ........... 103 ...............104...

  • Page 8: Signal Description

    88E3016 Integrated 10/100 Fast Ethernet Transceiver Section 1. Signal Description 1.1 88E3016 Device 64-Pin QFN Pinout The 88E3016 is manufactured in a 64-pin QFN. Figure 1: 88E3016 Integrated 10BASE-T/100BASE-TX Fast Ethernet Transceiver 64-Pin QFN Package RX_CTRL TSTPT RXD[0] MDIP[0] EPAD - VSS...

  • Page 9: Pin Description

    Input and output Input only Output only Internal pull up Internal pull down Open drain output Tri-state output DC sink capability Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 9...
  • Page 10 RGMII Receive Data. In RGMII mode, RXD[3:0] are used as RXD[2]/RD[2] RD[3:0]. RXD[1]/RD[1] RXD[0]/RD[0] The receive data nibble is presented on RXD[3:0] on the rising edge of RX_CLK. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 10 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 11 Section 2.11 "LED Interface" on page for LED interface details. LED[0] Parallel LED outputs. See Section 2.11 "LED Interface" on page for LED interface details. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 11...
  • Page 12 COMA Control. Active low. If RESETn is low then COMAn has no effect. COMAn contains an internal 150 kohm pull-up resistor. 0 = In power saving mode 1 = Normal operation Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 12 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 13 If debug is not important and there are board space constraints, this pin can be left floating. TSTPT Test point. Leave unconnected. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 13...
  • Page 14 3. VDDO supplies the SIGDET, MDC, MDIO, RESETn, LED[2:0], CONFIG[3:0], TDI, TMS, TCK, TRSTn, TDO, COMAn, DIS_REG12, CTRL25, HSDAC, and TSTPT pins. 4. VDDOR supplies the TXD[3:0], TX_CLK, TX_CTRL, RXD[3:0], RX_CLK, and RX_CTRL pins. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 14 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 15 0 = Low MDIO Active Active Active Tri-state Active Active Active Active Active High High High Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 15...

  • Page 16: 88E3016 64-Pin Qfn Assignments - Alphabetical By Signal Name

    88E3016 Integrated 10/100 Fast Ethernet Transceiver 1.2.2 88E3016 64-Pin QFN Assignments - Alphabetical by Signal Name Pin # Pin N ame Pin # Pin Name AVDD AVDDC AVDDR AVDDR RESETn AVDDX RSET COMAn RX_CLK CONFIG[0] RX_CTRL CONFIG[1] RXD[0] CONFIG[2] RXD[1]...

  • Page 17: Functional Description

    Functional Description Section 2. Functional Description Figure 2 shows the functional block for the 88E3016 device. The transmitter and transmit PCS block are fully described on page 21. The receiver and receive PCS block are fully described on page Figure 2: 88E3016 Device Functional Block Diagram...

  • Page 18: Reduced Gigabit Media Independent Interface (Rgmii)

    88E3016 Integrated 10/100 Fast Ethernet Transceiver 2.1 Reduced Gigabit Media Independent Interface (RGMII) The 88E3016 device supports the RGMII specification (Version 1.2a, 9/22/2000, version 2.0, 04/2002 - except instead of HSTL, it supports 2.5V SSTL_2). Figure 3: RGMII Signal Diagram...

  • Page 19: Serial Management Interface

    Read = 10 Device Register Turn- Write = 01 Address Address around Read = z0 Write = 10 11111111 01100 00000 0001001100000000 11111111 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 19...

  • Page 20: Preamble Suppression

    88E3016 Integrated 10/100 Fast Ethernet Transceiver 2.2.2 Preamble Suppression The 88E3016 devices are permanently programmed for preamble suppression. A minimum of one idle bit is required between operations. 2.2.3 Programming Interrupts When Register 22:11:8 is set to 1110, the interrupt functionality is mapped to the LED[2] pin.The interrupt function drives the LED[2] pin active whenever an interrupt event is enabled by programming register 18.

  • Page 21: Transmit And Receive Functions

    2.3.3.1 Analog to Digital Converter The 88E3016 device incorporates an advanced high speed ADC on each receive channel with greater resolution for better SNR, and therefore, lower error rates. Patented architectures and design techniques result in high differ- ential and integral linearity, high power supply noise rejection, and low metastability error rate.

  • Page 22: Decoder

    In 100BASE-FX mode the receive data stream is received and converted to NRZ. The decoding process is identi- cal to 100BASE-TX except no descrambling is necessary. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 22 Document Classification: Proprietary Information...

  • Page 23: Auto-Negotiation

    If Auto-Negotiation is enabled, then the 88E3016 devices negotiate with the link partner to determine the speed and duplex with which to operate. If the link partner is unable to Auto-Negotiate, the 88E3016 devices go into the parallel detect mode to determine the speed of the link partner. Under parallel detect mode, the duplex mode is fixed at half-duplex.

  • Page 24: Power Management

    When Register 16.14 is enabled, the Energy Detect +™ mode is enabled. In this mode, the PHY sends out a sin- gle 10 Mbps NLP (Normal Link Pulse) every one second. If the 88E3016 devices are in Energy Detect+ mode, it can wake a connected device.

  • Page 25: Coma Mode

    Note that if the power supply and reference clock requirements can be met then all registers will retain their values during the COMA state. Figure 6: XTAL_IN to COMAn Relationship RESETn COMAn XTAL_IN Toggling Not Toggling Toggling stop stop Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 25...

  • Page 26: Regulators And Power Supplies

    Integrated 10/100 Fast Ethernet Transceiver 2.5 Regulators and Power Supplies The 88E3016 device can operate from a single 2.5V or 3.3V supply if the regulators are used. If regulators are not used then a 2.5V and 1.2V supply are needed.

  • Page 27: Avddx

    DVDD is used as the 1.2V digital supply. DVDD can be supplied externally with 1.2V, or via the 1.2V regulator. All DVDD pins should be shorted together. A decoupling capacitor should be attached to pin 13 of the 88E3016 device.

  • Page 28: Hardware Configuration

    The LED, CRS, and COL outputs a bit stream during initialization that is used by the CONFIG pin inputs. The bit values are latched at the deassertion of hardware reset. The bit stream mapping for 88E3016 is shown in Table...
  • Page 29 MODE[0] Each bit in the configuration is defined as shown in Table Table 17: 88E3016 Configuration Definition B its D e f i n i t i o n B i ts A f f e c t e d...

  • Page 30: Far End Fault Indication (Fefi)

    2.8 802.3ah Unidirectional Enable The 88E3016 devices support the 802.3ah Unidirectional Enable function. When this function is enabled the PHY transmit path is enabled even if there is no link established. To enable unidirectional transmitting, all the following conditions must be met. Unidirectional is enabled (0.5 = 1). Auto-Negotiation is disabled (0.12 = 0). Full duplex enabled (0.8 = 1).

  • Page 31: Virtual Cable Tester® Feature

    TDR test can be performed either when there is no link partner or when the link partner is Auto-Negotiating or sending 10 Mbit idle link pulses. If the 88E3016 devices receive a continuous signal for 125 ms, it will declare test failure because it cannot start the TDR test.

  • Page 32: Auto Mdi/Mdix Crossover

    The Auto MDI/MDIX crossover function can be disabled via Register 16.5:4. The 88E3016 devices are set to MDI mode by default if auto MDI/MDIX crossover is disabled at hardware reset. The pin mapping in MDI and MDIX modes is specified in Table 19. Refer to...

  • Page 33: Led Interface

    10 = LED Off 11 = LED On 25.1:0 ForceLED0 00 = Normal 01 = Blink 10 = LED Off 11 = LED On Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 33...

  • Page 34: Phy Control

    1011 = ACT (Blink mode) 1100 = TX (Blink Mode) 1101 = RX (Blink Mode) 1110 = Interrupt 1111 = Force off Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 34 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 35 1011 = ACT (Blink mode) 1100 = TX (Blink Mode) 1101 = RX (Blink Mode) 1110 = COLX (Blink Mode) 1111 = Force off Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 35...
  • Page 36 1011 = ACT (Blink mode) 1100 = TX (Blink Mode) 1101 = RX (Blink Mode) 1110 = COLX (Blink Mode) 1111 = Force off Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 36 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 37 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Active for 100BASE-X 110 = Off 111 = Reserved Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 37...

  • Page 38: Led Polarity

    Some of the statuses indicate multiple events by blinking LEDs. The blink period can be programmed via Register 24.11:9. The default blink period is set to 84 ms. The blink rate applies to all applicable LEDs. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 38 Document Classification: Proprietary Information...

  • Page 39: Automatic And Manual Impedance Calibration

    Reserved Retain Latch 1 = Latch in new value. This bit self clears. R/W, Retain (Used for manual settings) Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 39...

  • Page 40: Changing Auto Calibration Targets

    To use manual calibration, write to the following registers: Write to register 29 = 0x000A Write to register 30 = b'000P PPPP 011N NNNN -- adjusts PMOS strength Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 40 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 41 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMOS Register Value (Decimal) Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance...
  • Page 42 10. After manual calibration, you see that the reflections are eliminated as in Figure Figure 10: Signal Reflections, using the 50 ohm Setting, 60 ohm line Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 42 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 43 Functional Description Automatic and Manual Impedance Calibration Figure 11: Clean signal after manual calibration for the 60 ohm Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 43...

  • Page 44: Crc Error Counter

    Integrated 10/100 Fast Ethernet Transceiver 2.13 CRC Error Counter The CRC counter, normally found in MACs, is available in the 88E3016 device. The error counter feature is enabled through register writes and the counter is stored in an eight bit register.

  • Page 45: Ieee 1149.1 Controller

    The bypass instruction uses the bypass register. The bypass register contains a single shift-register stage and is used to provide a minimum length serial path between the TDI and TDO pins of the 88E3016 device. This allows rapid movement of test data to and from other testable devices in the system.

  • Page 46: Extest Instruction

    The shifting of data for the sample and preload phases can occur simultaneously. While data capture is being shifted out, the preload data can be shifted in. One scan chain is available for the 88E3016 device. Table 26: 88E3016 Boundary Scan Chain Order...

  • Page 47: The Clamp Instruction

    Man ufa ctur er Id en tity Bit 31 to 28 Bit 27 to 12 Bit 11 to 1 0000 0000 0000 0010 0001 001 1110 1001 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 47...

  • Page 48: Register Description

    Note that in this context the setting of the page register (register 29) has no effect. Register 2 bit 3 is specified as 2.3. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 48 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 49 Value written to the register field does not take effect until soft reset is executed; however, the written value can be read even before the software reset. Write only. Reads to this type of register field return undefined data. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance...
  • Page 50 RGMII Output Impedance Calibration Override Register 30_10 Table 54, p. 76 RGMII Output Impedance Target Register 30_11 Table 55, p. 77 Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 50 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 51 If the AnegEn bit is set to 1, speed and duplex advertise- ment is found in the Auto-Negotiation Advertisement Register (Register 4). 0 = Disable Auto-Negotiation Process 1 = Enable Auto-Negotiation Process Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 51...
  • Page 52 0.12 = 0 and 0.8 = 1. Otherwise enable transmit direction only when valid link is established. Reserved Always Always Will always be 0. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 52 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 53 0 = Remote fault condition not detected 1 = Remote fault condition detected AnegAble Always Always Auto-Negotiation Ability Mode 1 = PHY able to perform Auto-Negotiation Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 53...
  • Page 54 0 = Jabber condition not detected 1 = Jabber condition detected ExtdReg Always Always Extended capability mode. 1 = Extended register capabilities Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 54 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 55 Model Number = 100010 100010 100010 RevNum Varies Varies Revision Number ® Contact Marvell FAEs for information on the device revision number. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 55...
  • Page 56 Values programmed into the Auto-Negotiation Adver- tisement Register have no effect unless Auto-Negotia- tion is restarted (RestartAneg 0.9) or link goes down. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 56 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 57 (RestartAneg 0.9) or link goes down. AnegAd Selec- Always Always Selector Field Mode 0x01 0x01 00001 = 802.3 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 57...
  • Page 58 LPTechAble 0x00 0x00 Technology Ability Field Received Code Word Bit 12:5 LPSelector 0x00 0x00 Selector Field Received Code Word Bit 4:0 Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 58 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 59 Received Code Word Bit 12 LPToggle Toggle Received Code Word Bit 11 10:0 LPData Message/Unformatted Field Received Code Word Bit 10:0 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 59...
  • Page 60 1 = A New Page has been received LPAnegAble Link Partner Auto-Negotiation Able 0 = Link Partner is not Auto-Negotiation able 1 = Link Partner is Auto-Negotiation able Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 60 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 61 Received Code Word Bit 12 RxToggle Toggle Received Code Word Bit 11 10:0 RxData 0x000 0x000 Message/Unformatted Field Received Code Word Bit 10:0 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 61...
  • Page 62 FEFI is automatically disabled regardless of the state of this bit if copper mode is selected. 0 = Enable FEFI 1 = Disable FEFI Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 62 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 63 Disable Jabber Jabber has no effect in full-duplex or in 100BASE-X mode. 0 = Enable jabber function 1 = Disable jabber function Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 63...
  • Page 64 Energy Detect Status 0 = Chip is not in sleep mode (Active) 1 = Chip is in sleep mode (No wire activity) Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 64 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 65 0 = Interrupt disable 1 = Interrupt enable FIFOErrInt Retain FIFO Over/Underflow Interrupt Enable 0 = Interrupt disable 1 = Interrupt enable Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 65...
  • Page 66 0 = Link status not changed 1 = Link status changed SymErrInt RO, LH Symbol Error 0 = No symbol error 1 = Symbol error Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 66 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 67 M o d e D e s c r i p t io n R s t R s t 15:0 Reserved 0x0000 0x0000 Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 67...
  • Page 68 1011 = ACT (Blink mode) 1100 = TX (Blink Mode) 1101 = RX (Blink Mode) 1110 = Interrupt 1111 = Force to 1 (inactive) Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 68 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 69 D e s c r i p t io n R s t R s t Reserved Always Always Must be 0. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 69...
  • Page 70 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Active for 100BASE-X 110 = Reserved 111 = Reserved Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 70 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 71 10 = LED Off 11 = LED On ForceLED0 Retain 00 = Normal 01 = Blink 10 = LED Off 11 = LED On Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 71...
  • Page 72 These bits are valid after completion of VCT (bit 15) and if the VCT test status bits (bit 14:13) have not indicated test failure. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 72 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 73 These bits are valid after completion of VCT (bit 15) and if VCT test status bits (bits 14:13) have not indicated test failure. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information...
  • Page 74 1 = Select Class A driver - available for 100BASE-TX mode only (typically used in Backplane or direct con- nect applications, but may be used with CAT 5 appli- cations) Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 74 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 75 30_9.0 is set Reserved Always 0x00 0000000 CRC Enable Retain 1=Enable CRC checker for all ports. 0=Disable CRC checker for all ports Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 75...
  • Page 76 Once LATCH is set to 1 the new calibration value is writ- ten into the I/O pad. The automatic calibrated value is lost. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 76 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 77 010 = 61 Ohm 011 = 54 Ohm 100 = 49 Ohm 101 = 44 Ohm 110 = 41 Ohm 111 = 38 Ohm Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 77...

  • Page 78: Electrical Specifications

    1. 125 °C is only used as bake temperature for not more than 24 hours. Long term storage (e.g weeks or longer) should be kept at 85 °C or lower. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 78 Document Classification: Proprietary Information...

  • Page 79: Recommended Operating Conditions

    1. Maximum noise allowed on supplies is 50 mV peak-peak. ® 2. Commercial operating temperatures are typically below 70 °C, e.g, 45 °C ~55 °C. The 70 °C max is Marvell specification limit 3. Refer to white paper on TJ Thermal Calculations for more information.

  • Page 80: Package Thermal Information

    88E3016 Integrated 10/100 Fast Ethernet Transceiver 4.3 Package Thermal Information 4.3.1 88E3016 Device 64-Pin QFN package Symb ol Para meter Con di ti on Un its θ °C/W Thermal resistance - JEDEC 3 in. x 4.5 in. 4-layer 32.40 junction to...

  • Page 81: Current Consumption

    100BASE-FX with traffic or idle COMA Sleep (Energy Detect+™) Power Down 1. The values listed are typical values with three LEDs and Auto-Negotiation on. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 81...

  • Page 82: Current Consumption Dvdd

    100BASE-FX with traffic or idle COMA Sleep (Energy Detect+™) Power Down 1. The values listed are typical values with three LEDs and Auto-Negotiation on. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 82 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 83: Dc Operating Conditions

    All pins capacitance 1. VDDO supplies the SIGDET, MDC, MDIO, RESETn, LED[2:0], CONFIG[3:0], TDI, TMS, TCK, TRSTn, TDO, COMAn, DIS_REG12, CTRL25, HSDAC, and TSTPT pins. Table 56: 88E3016 Device Internal Resistor Description 88 E3016 Pin Name Resisto r De vic e Pin #...

  • Page 84: Stub-Series Transceiver Logic (Sstl_2)

    This circuit can be used if termination is required. This circuit can also be used unterminated if the interconnect is short. Figure 13: SSTL_2 Input Voltage Levels VDDQ VIH(ac) VIH(dc) VREF VIL(dc) VIL(ac) Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 84 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 85 ± 1.0 V/ns Output Timing Reference Level VDDQ/2 VDDQ/2 ® 1. These numbers are preliminary. Marvell reserves the right to change these parameters. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information...

  • Page 86: Ieee Dc Transceiver Parameters

    (internal signal in 100BASE-TX mode). The will reject signals typically with peak-to-peak dif- ferential amplitude less than 360 mV. Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 86 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 87: Ac Electrical Specifications

    RESET Number of valid REFCLK clks SU_CLK cycles prior to RESETn de-asserted Figure 14: Reset Timing PU_RESET Power SU_CLK RESETn Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 87...

  • Page 88: Xtal_In Input Clock Timing

    3. Broadband peak-peak = 200 ps, Broadband rms = 3 ps, 12 kHz to 20 MHz rms = 1 ps. Figure 15: Clock Timing P_XTAL_IN H_XTAL_IN L_XTAL_IN XTAL_IN Input R_XTAL_IN F_XTAL_IN Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 88 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 89: Rgmii Interface Timing

    L_RGMII_ TX_CLK TX_CLK Period P_RGMII_ TX_CLK Figure 16: RGMII Transmit Timing p_rgmii_tx_clk TX_CLK l_rgmii_tx_clk h_rgmii_tx_clk TXD[3:0], TX_CTL hd_rgmii_tx_clk hd_rgmii_tx_clk su_rgmii_tx_clk su_rgmii_tx_clk Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 89...

  • Page 90: Rgmii Receive Timing

    RGMII Output to Clock SU_RGMII_ RX_CLK RGMII Clock to Output HD_RGMII_ RX_CLK RX_CLK High H_RGMII_ RX_CLK RX_CLK Low L_RGMII_ RX_CLK RX_CLK Period P_RGMII_ RX_CLK Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 90 Document Classification: Proprietary Information January 4, 2008, Advance...
  • Page 91 Figure 18: RGMII RX_CLK Delay Timing - Register 28.11:10 = 01 (add delay) p_rgmii_rx_clk RX_CLK l_rgmii_rx_clk h_rgmii_rx_clk RXD[3:0], RX_CTL hd_rgmii_rx_clk hd_rgmii_rx_clk su_rgmii_rx_clk su_rgmii_rx_clk Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 91...

  • Page 92: Latency Timing

    10BASE-T TX_CTRL 2245 2360 DA_TXC_ De-asserted to ETD MDI_10 Figure 19: RGMII to 10/100 Transmit Latency Timing TX_CLK TX_CTRL PREAMBLE AS_TXC_MDI DA_TXC_MDI Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 92 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 93: 100Base-Tx To Rgmii Receive Latency Timing

    10BASE-T MDI ETD to 1300 1910 DA_MDI_ RX_CTRL De-asserted RXC_10 Figure 20: 10/100 to RGMII Receive Latency Timing PREAMBLE RX_CTRL RX_CLK AS_MDI_RXC DA_MDI_RXC Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 93...

  • Page 94: Serial Management Timing

    MDC Low L_ MDC Figure 21: Serial Management Timing H_MDC L_MDC P_MDC DLY_MDIO MDIO (Output) HD_MDIO SU_MDIO Valid Data MDIO (Input) Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 94 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 95: Jtag Timing

    TDI, TMS to TCK Hold Time HD_TDI TCK to TDO Delay DLY_TDO Figure 22: JTAG Timing P_TCK L_TCK H_TCK HD_TDI SU_TDI DLY_TDO Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information Page 95...

  • Page 96: Package Mechanical Dimensions

    88E3016 Integrated 10/100 Fast Ethernet Transceiver Section 5. Package Mechanical Dimensions 5.1 88E3016 Package Mechanical Dimensions Figure 23: 88E3016 64-pin QFN package 1.0mm DETAIL : B ''B'' 0.08 C SEATING PLANE 0.6max "A" DETAIL : A Doc. No. MV-S103164-00, Rev. A Copyright ©...
  • Page 97 Package Mechanical Dimensions 88E3016 Package Mechanical Dimensions Table 58: 64-Pin QFN Mechanical Dimensions D i m e n s io n s i n m m Sy m b o l M IN N O M M A X 0.80 0.85...

  • Page 98: Application Examples

    MDIN[1] Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω Ω Ω Ω Ω 49.9 49.9 μ 0.01 1000pF 3 kV Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 98 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 99: Fx Interface To 3.3V Fiber Transceiver

    MDIP[1] 0.01 uF MDIN[1] Ω Ω SIGDET Terminate at 88E3016 inputs TBD -- To be determined by the application of the fiber module. Copyright © 2008 Marvell Doc. No. MV-S103164-00, Rev. A January 4, 2008, Advance Document Classification: Proprietary Information...

  • Page 100: Transmitter - Receiver Diagram

    Sink 15 mA 2.36 + 1.62 Common mode: = 2V ® ® Marvell 100BASE-FX PHY Marvell 100BASE-FX PHY Transmitter Receiver Doc. No. MV-S103164-00, Rev. A Copyright © 2008 Marvell Page 100 Document Classification: Proprietary Information January 4, 2008, Advance...

  • Page 101: 88E3016 To 88E3016 Backplane Connection - 100Base-Fx Interface

    Application Examples 88E3016 to 88E3016 Backplane Connection - 100BASE-FX Interface 6.4 88E3016 to 88E3016 Backplane Connection - 100BASE-FX Interface Figure 27: 88E3016 to 88E3016 Backplane Connection - 100BASE-FX Interface 3.3V 3.3V Ω Ω Ω Ω 0.01 uF MDIP[0] MDIN[0] 0.01 uF Ω...

  • Page 102: 88E3016 To Another Vendor's Phy - 100Base-Fx Interface Through A Backplane102

    88E3016 Integrated 10/100 Fast Ethernet Transceiver 6.5 88E3016 to Another Vendor’s PHY - 100BASE-FX Inter- face through a Backplane Figure 28: 88E3016 to Another Vendor’s PHY - 100BASE-FX Interface through a Backplane 3.3V 3.3V Ω Ω 0.01 uF MDIP[0] MDIN[0] 0.01 uF...

  • Page 103: Marvell® Phy To Marvell Phy Direct Connection

    Application Examples Marvell® PHY to Marvell PHY Direct Connection ® 6.6 Marvell PHY to Marvell PHY Direct Connection ® Figure 29: Marvell PHY to Marvell PHY Direct Connection 3.3V Ω Ω MDIP[1] MDIP[0] MDIN[1] MDIN[0] Ω Ω 3.3V 88E3016 88E3016 Ω...

  • Page 104: Order Information

    Section 7. Order Information 7.1 Ordering Part Numbers and Package Markings ® Figure 30 shows the ordering part numbering scheme for the 88E3016 device. Contact Marvell FAEs or sales representatives for complete ordering information. Figure 30: Sample Part Number – xx – xxx – C000 - T123...
  • Page 105 Ordering Part Numbers and Package Markings Figure 31 is an example of the package marking and pin 1 location for the 88E3016 64-pin QFN commercial RoHS 5/6 compliant package. Figure 31: 88E3016 64-pin QFN Commercial RoHS 5/6 Compliant Package Marking and Pin 1...
  • Page 106 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster...

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