88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Figure 26: 10/100 to MII Receive Latency Timing
/J/
100
10
PREAMBLE
CRS
COL
RX_CTRL
Note
This diagram assumes that the device was already transmitting data when data has started to be received
from the link partner. In half-duplex mode this will cause a collision. Compare this figure with
Doc. No. MV-S103657-00, Rev. D
Page 108
/K/
T
AS_MDI_CRS
T
AS_MDI_COL
T
AS_MDI_RXCTRL
Document Classification: Proprietary Information
/T/
/R/
ETD
T
DA_MDI_CRS
T
DA_MDI_COL
T
DA_MDI_RXCTRL
Figure
Copyright © 2008 Marvell
January 4, 2008, Advance
25.