Marvell 88E3015 Manual page 4

88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
MDIP/N[0]
MDIP/N[1]
SIGDET
XTAL_IN
XTAL_OUT
RESETn
COMAn
CTRL25
DIS_REG12
JTAG
MDIP/N[0]
MDIP/N[1]
SIGDET
XTAL_IN
XTAL_OUT
RESETn
COMAn
CTRL25
DIS_REG12
Table 1:
Package
MII
RGMII
Virtual Cable Tester
Fiber Support
Parallel LEDs
Power Management
JTAG Support
Industrial Grade
Doc. No. MV-S103657-00, Rev. D
Page 4
DAC
Auto MDIX
Crossover
10 Mbps
FX Link
Receiver
& Auto
Negotiation
Digital
ADC Adaptive
Equalizer
Clock/
Reset
Baseline
Wander
Canceller
2.5V
Regulator
1.2V
Regulator
88E3015 Device Functional Block Diagram
Boundary
Scan
DAC
Auto MDIX
10 Mbps
Crossover
Receiver
Digital
FX Link
ADC Adaptive
& Auto
Equalizer
Negotiation
Baseline
Wander
Canceller
Clock/
Reset
2.5V
Regulator
1.2V
Regulator
88E3018 Device Functional Block Diagram
88E3015/88E3018 Devices Feature Differences
88E30 15
56-pin QFN
Yes
Yes
®
Yes
Yes
Yes
Yes
No
No
Document Classification: Proprietary Information
VREF
CRS
10/100 COL
Transmit
TXD[3:0]
PCS
TX_CTRL
RGMII
TX_CLK
or MII
10/100
RXD[3:0]
Receive
RX_CTRL
PCS
RX_CLK
RX_ER
MDC
Management
Interface
MDIO
LED[2:0]
LED/
Configuration
CONFIG[3:0]
VREF
10/100
CRS
Mbps
COL
Transmit
PCS
TXD[3:0]
TX_CTRL
RGMII
TX_CLK
10/100
or MII
Mbps
Receive
RXD[3:0]
PCS
RX_CTRL
RX_CLK
RX_ER
MDC
Management
Interface
MDIO
LED[2:0]
LED/
Configuration
CONFIG[3:0]
8 8E301 8
64-pin QFN
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS 6/6 Package Only
Copyright © 2008 Marvell
January 4, 2008, Advance