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88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Sample allows a snapshot to be taken of the data flowing from the system pins to the on-chip test logic or vice
versa, without interfering with normal operation. The snapshot is taken on the rising edge of TCK in the Capture-
DR controller state, and the data can be viewed by shifting through the component's TDO output.
While sampling and shifting data out through TDO for observation, preload allows an initial data pattern to be
shifted in through TDI and to be placed at the latched parallel output of the boundary-scan register cells that are
connected to system output pins. This ensures that known data is driven through the system output pins upon
entering the extest instruction. Without preload, indeterminate data would be driven until the first scan sequence is
complete. The shifting of data for the sample and preload phases can occur simultaneously. While data capture is
being shifted out, the preload data can be shifted in.
One scan chain is available for the 88E3018 devices.
Table 28:
88E3018 Boundary Scan Chain Order
PI N
I/ O
MDIO
Output Enable
MDIO
Output
MDIO
Input
MDC
Input
(RGMII)
Output Enable
RX_CTRL
Output
RXD[0]
Output
RXD[1]
Output
RX_CLK
Output
RXD[2]
Output
RXD[3]
Output
TXD[0]
Input
TXD[1]
Input
TX_CLK
Input
TXD[2]
Input
TXD[3]
Input
TX_CTRL
Input
CONFIG[0]
Input
CONFIG[1]
Input
CONFIG[2]
Input
CONFIG[3]
Input
LED[0]
Output Enable
LED[0]
Output
LED[1]
Output Enable
LED[1]
Output
LED[2]
Output Enable
LED[2]
Output
COMAn
Input
RESET
Input
SIGDET
Input
Doc. No. MV-S103657-00, Rev. D
Page 54
Document Classification: Proprietary Information
Copyright © 2008 Marvell
January 4, 2008, Advance
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