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Marvell 88E1111 Manual

Integrated 10/100/1000 ultra gigabit ethernet transceiver
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Marvell
88E1111
Integrated 10/100/1000 Ultra
Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. A
December 02, 2020
Document Classification: Proprietary Information
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Summary of Contents for Marvell 88E1111

  • Page 1 ® Marvell 88E1111 Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Doc. No. MV-S105540-00, Rev. A December 02, 2020 Document Classification: Proprietary Information Cover...
  • Page 2 Marvell products are not authorized for use as critical components in medical devices, military systems, life or critical support devices, or related systems. Marvell is not liable, in whole or in part, and the user will indemnify and hold Marvell harmless for any claim, damage, or other liability related to any such use of Marvell products.
  • Page 3 Auto-Calibration for MAC Interface outputs power dissipation. • Requires only two supplies: 2.5V and 1.0V (with The 88E1111 device is offered in three different pack- 1.2V option for the 1.0V supply) age options including a 117-Pin TFBGA, a 96-pin aQFN •...
  • Page 4 Gigabit Ethernet 3-Speed Device Serial Interface MAC Interface Options - 4-pin SGMIII - GMII - RGMII 88E1111 RGMII/GMII MAC to SGMII MAC Conversion Doc. No. MV-S105540-00, Rev. A Copyright © 2020 Marvell December 2, 2020 Page 4 Document Classification: Proprietary Information...

  • Page 5: Table Of Contents

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table of Contents 117-Pin TFBGA Package....................6 96-Pin aQFN Package ....................7 128-Pin PQFP Package ....................9 Pin Description ......................10 1.4.1 Pin Type Definitions......................10 I/O State at Various Test or Reset Modes ..............35 117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name .....36...

  • Page 6: 117-Pin Tfbga Package

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Section 1. Signal Description The 88E1111 device is a 10/100/1000BASE-T/1000BASE-X Gigabit Ethernet transceiver. 1.1 117-Pin TFBGA Package Figure 1: 88E1111 Device 117-Pin TFBGA Package (Top View) LED_ RXD5 RXD6 S_IN+ S_IN-...

  • Page 7: 96-Pin Aqfn Package

    Signal Description 96-Pin aQFN Package 96-Pin aQFN Package Figure 3: 88E1111 Device 96-Pin BCC Package (Top View) - (OBSOLETE - No Longer Available - Replaced by 96-Pin aQFN Package) LED_LINK VDDOX S_OUT- TRSTn LED_LINK S_OUT+ AVDD AVDD S_CLK+ MDI[3]- S_CLK-...
  • Page 8 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Figure 4: 88E1111 Device 96-Pin aQFN Package (Top View) LED_LINK VDDOX S_OUT- TRSTn LED_LINK EPAD - VSS S_OUT+ AVDD AVDD S_CLK+ MDI[3]- S_CLK- MDI[3]+ S_IN- MDI[2]- S_IN+ AVDD MDI[2]+ HSDAC- DVDD...

  • Page 9: 128-Pin Pqfp Package

    Signal Description 128-Pin PQFP Package 1.3 128-Pin PQFP Package Figure 5: 88E1111 Device 128-Pin PQFP Package (Top View) AVDD AVDD S_OUT- MDI[3]- MDI[3]+ S_OUT+ AVDD S_CLK- S_CLK+ MDI[2]- MDI[2]+ S_IN- S_IN+ HSDAC- HSDAC+ AVDD DVDD DVDD AVDD 88E1111 - RCJ...

  • Page 10: Pin Description

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 1.4 Pin Description 1.4.1 Pin Type Definitions Pi n Ty pe De fin iti on Input with hysteresis Input and output Input only Output only Internal pull up Internal pull down...
  • Page 11 MDI configuration, MDI[1]± are used for the receive pair. In MDIX configuration, MDI[1]± are used for the transmit pair. MDI[1]± should be tied to ground if not used. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information...
  • Page 12 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 1: Media Dependent Interface (Continued) 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name De scrip tio n Pin # P i n # Pin # Typ e...
  • Page 13 TX_EN de-asserted, carrier extension symbol is transmitted onto the cable. TX_ER is synchronous to GTX_CLK, and synchronous to TX_CLK in 100BASE-TX and 10BASE-T modes. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 13...
  • Page 14 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 2: GMII/MII Interfaces (Continued) 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name Des cription Pin # P i n # Pin # Ty pe TXD[7] GMII and MII Transmit Data. In GMII mode,...
  • Page 15 (SQE). SQE can be disabled by clearing reg- ister 16.2 to zero. COL is asynchronous to RX_CLK, GTX_CLK, and TX_CLK. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 15...
  • Page 16 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII interface. The MAC interface pins are 3.3V tolerant. Table 3: TBI Interface 117 -T F B GA...
  • Page 17 If this feature is not used, the COL pin should be driven low on the board. This pin should not be left floating in TBI mode. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information...
  • Page 18 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver The RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface pins are also used for the RTBI interface. See Table 5 for RTBI pin definitions. The MAC interface pins are 3.3V tolerant.
  • Page 19 In RGMII 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on the rising edge of RX_CLK. RXD[3:0] are synchronous to RX_CLK. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 19...
  • Page 20 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the RGMII interface. The MAC interface pins are 3.3V tolerant. Table 5: RTBI Interface 117 -T F B GA...
  • Page 21 26.5. Output amplitude can be adjusted via register 26.2:0. The output impedance default setting is determined by the 75/50 OHM configura- tion pin. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 21...
  • Page 22 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 7: 1.25 GHz Serial High Speed Interface 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name De scr ip tio n Pin # P i n # Pin #...
  • Page 23 O, Z Serial MAC interface PHY_SIGDET[0] con- nection. 1 = S_OUT± invalid 0 = S_OUT± valid code groups according to clause 36 Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 23...
  • Page 24 Pin # Typ e MDC/SCL Two-Wire Serial Interface (TWSI) serial clock line. When the 88E1111 device is con- nected to the bus, MDC connects to the serial clock line (SCL). Data is input on the rising edge of SCL, and output on the falling edge.
  • Page 25 LED_LINK10, LED_LINK100, and LED_LINK1000 must be read together to determine link and speed status. LED_LINK10 is a multi-function pin used to configure the 88E1111 device at the de- assertion of hardware reset. LED_LINK100 O, mA Parallel LED output for 100BASE-TX link or speed.
  • Page 26 1000 Mbps link up or down. In combined LED mode, the output from LED_LINK1000 indicates link status. LED_LINK1000 is a multi-function pin used to configure the 88E1111 device at the de- assertion of hardware reset. LED_DUPLEX O, mA Parallel LED duplex or duplex/collision modes.
  • Page 27 Mode 2 Low = Link up High = Link down Blink = Receiving LED_RX is a multi-function pin used to con- figure the 88E1111 device at the de-asser- tion of hardware reset. LED_TX O, mA Parallel LED Transmit Activity or RX/TX Activity/Link modes.
  • Page 28 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 11: JTAG Interface 117-T FBGA 9 6- aQ FN 128 -PQF P Pi n Typ e P i n Des cription P i n # Pin # P i n #...
  • Page 29 For the TWSI device address, the lower 5 bits, which are PHYADR[4:0], are latched during hardware reset, and the device address bits [6:5] are fixed at ‘10’. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information...
  • Page 30 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 12: Clock/Configuration/Reset/I/O (Continued) 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name De scr ip tio n Pin # P i n # Pin # Typ e CONFIG[2] CONFIG[2] pin configures ANEG[3:1] bits.
  • Page 31 COMA pin. To deactivate the COMA power mode, tie the COMA pin low. Upon deactivating COMA mode, the 88E1111 device will continue normal operation. The COMA power mode cannot be enabled as long as hardware reset is enabled.
  • Page 32 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 13: Test 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name De scr ip tio n Pin # P i n # Pin # Typ e HSDAC+ Analog Test pins.
  • Page 33 Power 2.5V Supply for the MDC/MDIO, INTn, 125CLK, RESETn, JTAG pin Power. VDDO Power 2.5V I/O supply for the MAC interface pins. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 33...
  • Page 34 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 15: Power & Ground (Continued) 117 -T F B GA 96-aQFN 1 28-PQF P Pin Name De scr ip tio n Pin # P i n # Pin # Typ e...

  • Page 35: I/O State At Various Test Or Reset Modes

    0 = Toggle 1 = Low 1 = Low 1 = Low can be either 1 = Low high or low 0 = Low Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 35...

  • Page 36: 117-Pin Tfbga Pin Assignment List - Alphabetical By Signal Name

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name P i n # P i n N a m e Pin # Pin Name 125CLK LED_LINK1000 AVDD LED_RX AVDD...
  • Page 37 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TX_CLK TX_EN TX_ER VDDO VDDO VDDO VDDOH VDDOH VSSC VDDOH XTAL1 VDDOX XTAL2 VDDOX Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 37...

  • Page 38: 96-Pin Aqfn Pin Assignment List - Alphabetical By Signal Name

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 1.7 96-Pin aQFN Pin Assignment List - Alphabetical by Sig- nal Name NOTE: The 96-pin BCC package is obsolete and is no longer available. The 96-Pin aQFN package is a pin compatible replacement for the 96-Pin BCC package.
  • Page 39 VDDO VDDO VDDO VDDOH TRSTn VDDOH TXD0 VDDOH TXD1 VDDOX TXD2 VDDOX TXD3 EPAD EPAD TXD4 VSSC TXD5 XTAL1 TXD6 XTAL2 TXD7 Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 39...

  • Page 40: 128-Pin Pqfp Pin Assignment List - Alphabetical By Signal Name

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 1.8 128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name P i n # P i n N a m e Pin # Pin Name 125CLK INTn AVDD LED_DUPLEX AVDD...
  • Page 41 TX_EN TX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 VDDO VDDO VDDO VDDO VDDOH VDDOH VDDOH VDDOX VSSC VDDOX XTAL1 XTAL2 Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 41...

  • Page 42: 117-Pin Tfbga Package

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Section 2. Package Mechanical Dimensions 2.1 117-pin TFBGA Package (All dimensions in mm.) Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Page 42 Document Classification: Proprietary Information...
  • Page 43 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information...

  • Page 44: 96-Pin Bcc Package - Top View - Obsolete - No Longer Available - Replaced By The 96- Pin Aqfn Package

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 2.2 96-pin BCC Package - Top View - OBSOLETE - No Lon- ger Available - Replaced by the 96-Pin aQFN Package Note The 96-Pin aQFN package is a pin compatible replacement for the 96-Pin BCC package. See Product...

  • Page 45: 96-Pin Bcc Package - Bottom View - Obsolete - No Longer Available - Replaced By The 96-Pin Aqfn Package

    3.50 0.60±0.10 ''A'' (PIN 1 CORNER) 0.600 TYP. 4.800 CL.(PKG.) "B" 0.30±0.05 7.00 0.08 7.200 8.20 DETAIL "B" (95X) 9.00 BOTTOM VIEW Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 45...

  • Page 46: 96-Pin Aqfn Package - Top View

    88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver 2.4 96-pin aQFN Package - Top View TOP VIEW PIN 1 CORNER SECTIONC-C SECTIONC-C Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Page 46 Document Classification: Proprietary Information...

  • Page 47: 96-Pin Aqfn Package - Bottom View

    2.400 0.000 DETAIL "A" 2:1 (96X) C.L(PKG.) 2.400 2.700 2.800 2.900 "A" 3.000 3.300 3.500 3.600 4.100 PKG. 4.500 PIN 1 CORNER Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 47...
  • Page 48 88E1111 Product Brief Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Table 17: 96-Pin aQFN Package Dimensions Co ntr ol li ng Dim ens io n: MM S y m b o l MI N NO M M A X 0.85 0.020 0.050...

  • Page 49: 128-Pin Pqfp Package

    0.10 ± 14.00 0.10 ± 17.20 0.20 PIN1 INDICATOR 1.6 Nominal 3.40 Max 0.25 ± ± 0.22 0.05 0.88 0.15 0.5 Basic Copyright © 2020 Marvell Doc. No. MV-S105540-00, Rev. A December 2, 2020 Document Classification: Proprietary Information Page 49...

  • Page 50: Ordering Part Numbers And Package Markings

    Section 3. Order Information 3.1 Ordering Part Numbers and Package Markings ® Figure 6 shows the ordering part numbering scheme for the 88E1111 devices. Contact Marvell FAEs or sales representatives for complete ordering information. Figure 6: Sample Part Number 88E1111 –...

  • Page 51: Rohs 5/6 Compliant Marking Examples

    3.1.1 RoHS 5/6 Compliant Marking Examples Figure 7 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial RoHS 5/6 compliant package. Figure 7: 88E1111 117-pin TFBGA Commercial RoHS 5/6 Compliant Package Marking and Pin...
  • Page 52 Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Figure 8 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA Industrial RoHS 5/6 compliant package. Figure 8: 88E1111 117-pin TFBGA Industrial RoHS 5/6 Compliant Package Marking and Pin 1...

  • Page 53: Rohs 6/6 Compliant Marking Examples

    3.1.2 RoHS 6/6 Compliant Marking Examples Figure 10 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial RoHS 6/6 compliant package. Figure 10: 88E1111 117-pin TFBGA Commercial RoHS 6/6 Compliant Package Marking and Pin...
  • Page 54 Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver Figure 12 is an example of the package marking and pin 1 location for the 88E1111 128-pin PQFP Commercial RoHS 6/6 compliant package. Figure 12: 88E1111 128-pin PQFP Commercial RoHS 6/6 Compliant Package Marking and Pin 1...

  • Page 55: Green Compliant Marking Examples

    Note: The above example is not drawn to scale. Location of markings is approximate. Figure 14 is an example of the package marking and pin 1 location for the 88E1111 96-pin aQFN Industrial Green compliant package. Figure 14: 88E1111 96-pin aQFN Industrial Green Compliant Package Marking and Pin 1 Loca-...
  • Page 56 For more information, visit www.marvell.com. © 2020 Marvell. All rights reserved. The MARVELL mark and M logo are registered and/or common law trademarks of Marvell and/or its Affiliates in the US and/or other countries. This document may also contain other registered or common law trademarks of Marvell and/or its Affiliates.

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