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88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Table 31:
Register Map
R e g is t er N a m e
PHY Control Register
PHY Status Register
PHY Identifier
PHY Identifier
Auto-Negotiation Advertisement Register
Link Partner Ability Register (Base Page)
Link Partner Ability Register (Next Page)
Auto-Negotiation Expansion Register
Next Page Transmit Register
Link Partner Next Page Register
PHY Specific Control Register
PHY Specific Status Register
PHY Interrupt Enable
PHY Interrupt Status
PHY Interrupt Port Summary
Receive Error Counter
LED Parallel Select Register
PHY LED Control Register
PHY Manual LED Override
VCT™ Register for MDIP/N[0] Pins
VCT™ Register for MDIP/N[1] Pins
PHY Specific Control Register II
Test Mode Select
CRC Status Register
MAC Interface Output Impedance Calibration Override
MAC Interface Output Impedance Target
Doc. No. MV-S103657-00, Rev. D
Page 58
R e g i s t e r A d d r e s s
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 5
Register 6
Register 7
Register 8
Register 16
Register 17
Register 18
Register 19
Register 20
Register 21
Register 22
Register 24
Register 25
Register 26
Register 27
Register 28
Register 29
Register 30_9
Register 30_10
Register 30_11
Document Classification: Proprietary Information
Ta b l e a n d P a g e
Table 32, p. 59
Table 33, p. 61
Table 34, p. 63
Table 35, p. 63
Table 36, p. 64
Table 37, p. 66
Table 38, p. 67
Table 39, p. 68
Table 40, p. 69
Table 41, p. 69
Table 42, p. 70
Table 43, p. 72
Table 44, p. 73
Table 45, p. 75
Table 46, p. 76
Table 47, p. 76
Table 48, p. 77
Table 49, p. 79
Table 50, p. 80
Table 51, p. 81
Table 52, p. 82
Table 53, p. 83
Table 54, p. 84
Table 55, p. 84
Table 56, p. 85
Table 57, p. 86
Copyright © 2008 Marvell
January 4, 2008, Advance
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