Marvell ARMADA 88F6810 Manuals

Manuals and User Guides for Marvell ARMADA 88F6810. We have 1 Marvell ARMADA 88F6810 manual available for free PDF download: Hardware Design Manual

Marvell ARMADA 88F6810 Hardware Design Manual (163 pages)

38x Family High-Performance Sing

Brand: Marvell | Category: Computer Hardware | Size: 1.38 MB

Table of Contents
4
Revision History
13
Introduction
13
Table 1: Revision History
13
Table 1: Related Documents
14
4-Layer Board Recommendations
15
Stack-Up Example
15
Table 2: 4-Layer Stack up Example
15
General Guidelines
16
88F6810, 88F6820 and 88F6828 Power Filtering
17
Routing Guidelines for the ISET Signal
18
Board Recommendations for Stripline Routing PCB
18
Table 3: List of Capacitors
18
Generic Guidelines for SERDES Interfaces
19
Insertion Loss and Loss Budget
19
Figure 1: Insertion Loss Curve
20
Inter-Symbol Interference (ISI)
22
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI
22
Figure 3: Difference in Attenuation Due to ISI - Time Domain Influence
23
Figure 4: ISI Originated Jitter - Eye Pattern
23
Placement of Devices and Connectors on the Board
24
PCB Materials Selection
25
Crosstalk
26
Figure 5: Stack-Up Cross-Section with a High Probability of Crosstalk
27
Return Path Continuity
28
Figure 6: Non-Continuous Reference Plane Return Current Path Influence
29
Figure 7: Layer Transfer
29
Target Routing Impedance
30
Figure 8: Reference Plane Clearance
31
Figure 9: Changed Width for Differential Impedance Compensation
32
Capacitive Discontinuities
33
Figure 10: Voids Underneath AC Coupling Capacitors' Pads
33
Figure 11: Voids Underneath BGA Device Ball
34
Figure 12: Voids Underneath SMT Connector/Qfp Lead Frame Pads
34
Trace Symmetry and Matching-Mode Conversion
35
Via Structures
35
Figure 13: Proper Deskew
35
Figure 14: Via Structures
36
Figure 15: Via Stubs
37
Figure 16: Differential Via Structure
37
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps
38
Selecting the Appropriate Components
39
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces
39
Generic Power Board Guidelines
40
Generic Power Network Guidelines
40
DC Voltage Drop
41
Polygon Shape Considerations
41
Figure 19: Coupling of Vias
41
Figure 20: Routing Length between the Capacitor and the Vias
41
Analog Power Filtering
42
Figure 21: Required Analog Power Filter Voltage Transfer Function
42
Figure 22: Analog Power Filter Example
43
Table 4: Definition of Analog Power Filter Symbols
43
Core Power Decoupling
44
I/O Power Bypassing
44
Bulk Capacitors
45
Figure 23: Return Path Discontinuity-Bypass Capacitor
45
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins
45
Termination Voltage (VTT) Layout Recommendations
46
Unused Interface
47
JTAG Connection Information
48
Figure 25: JTAG Connection
48
16-Bit SDRAM DDR3 Interface
49
Interface Connectivity
49
Table 5: Signal Groups
50
Figure 26: on Board 1X16-Bit Wide Memory Device with ECC Connected to the Controller
51
Figure 27: on Board 2X8-Bit Wide Memory Devices with ECC Connected to the Controller
52
Figure 28: on Board 16-Bit, 4X8-Bit Wide Memory Devices with ECC Connected to the Controller
53
Interface Signals Layout Guidelines
54
Figure 29: on Board 16-Bit, 1X16-Bit Wide Memory with ECC Topology-Address and Control
55
Figure 30: on Board 16-Bit, 1X16-Bit Single-Side Assembly Topology with ECC-Data
56
Table 6: Routing Constraints When Using on Board 16-Bit, 1X16-Bit Wide Memory Topology
57
Figure 31: on Board 16-Bit, 2X8-Bit Wide Memory Topology with ECC -Address
58
Figure 32: On-Board 16-Bit, 2X8-Bit with ECC, Single-Side Assembly Topology-Data
59
Table 7: Routing Constraints-On-Board 16-Bit, 2X8-Bit Topology
60
Figure 33: on Board 16-Bit, 4X8-Bit Wide Memory Topology for Clock/Address/Command/Control with
62
Figure 34: on Board 16-Bit, 4X8-Bit Wide Memory with ECC Topology for Data
63
Table 8: Routing Constraints When Using on Board 16-Bit, 4X8-Bit Wide Memory Topology Using a
64
Special Software Setting
65
Table 9: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select
65
Table 10: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly
65
32-Bit SDRAM DDR3 Interface
66
Interface Connectivity
66
Table 11: Signal Groups
66
Figure 35: On-Board 32-Bit 2 Memory Devices, 2X16-Bit Single-Side Connectivity
68
Figure 36: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity
69
Figure 37: On-Board 32-Bit, 8X8-Bit Clamshell Connectivity with ECC
70
Interface Signals Layout Guidelines
71
Figure 38: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology-Address and Control with ECC
72
Figure 39: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology with ECC-Data
73
Table 12: Routing Constraints-32-Bit, 2X16-Bit Single Side Assembly Topology
73
Figure 40: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control
76
Figure 41: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data
77
Table 13: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology
78
Figure 42: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Address and Control
80
Figure 43: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Data
81
Table 14: Routing Constraints-On-Board 32-Bit with or Without ECC, 8X8-Bit Clamshell Topology
81
Power Signals
83
Special Software Setting
83
Table 15: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select
83
Table 16: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly
84
32-Bit SDRAM DDR4 Interface
85
Interface Connectivity
85
Figure 44: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity
87
Interface Signals Layout Guidelines
88
Figure 45: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control
90
Figure 46: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data
91
Table 18: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology
92
Power Signals
93
Special Software Setting
94
Table 19: ODT Control Matrix for SDRAM DDR4 with 1 Chip Select
94
Network Ethernet Ports
95
Reduced Gigabit Media Independent Interface (RGMII)
96
Interface Connectivity
96
Connectivity
96
Interface Signals Layout Guidelines
97
Figure 47: RGMII Port Connection to PHY
97
Figure 48: RGMII Port Connection to Another RGMII MAC
97
Figure 49: RGMII Routing Topology
98
Table 21: no Internal Delay on Transmitting or on Receiving Peer Side-Tx Path
98
Table 22: Internal Delay on Transmitting or on Receiving Peer Side-Tx Path
99
Table 23: no Internal Delay on Receiving or on Transmitting Peer Side-Rx Path
100
Table 24: Internal Delay on Receiving or on Transmitting Peer Side-Rx Path
100
Serial Gigabit Media Independent Interface (SGMII)
101
Interface Connectivity
101
Figure 50: SGMII Generic Point-To-Point Connection
101
Table 17: Signal Groups
101
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection
102
Figure 51: SGMII Topology for Chip-To-Chip, End-To-End Connection
102
Table 26: Routing Constraints Chip-To-Chip, End-To-End Connection
102
Power Considerations
104
Specific Signals
104
High Speed Serial Gigabit Media Independent Interface (HS-SGMII)
105
Interface Connectivity
105
Figure 52: SGMII Generic Point-To-Point Connection
105
Table 20: Signal Groups
105
Interface Signals Layout Guidelines
106
Figure 53: Topology for Chip-To-Chip, End-To-End Connection
106
Table 28: Routing Constraints for a Chip-To-Chip End-To-End Connection
106
Power Considerations
108
Specific Signals
108
Quad Serial Gigabit Media Independent Interface (QSGMII)
109
Interface Connectivity
109
Figure 54: QSGMII Generic Point-To-Point Connection
109
Table 29: Signal Groups
109
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection
110
Figure 55: QSGMII Topology for Chip-To-Chip, End-To-End Connection
110
Table 30: Routing Constraints for a Chip-To-Chip End-To-End Connection Topology
110
Clock Considerations
112
Power Considerations
112
Specific Signals
112
PCI Express (Pcie) Interface 1.0/1.1
113
Connectivity
113
Table 31: Signal Groups
113
Table 32: Specific Device
113
Figure 56: PCI Express Interface Connectivity
114
Device
114
Interface Signals Layout Guidelines
115
Figure 58: Topology with an Existing Connector And/Or an Add-In Card
115
Table 33: System Board with Existing Connector
116
Table 34: Add-In Card
117
Figure 59: Topology with a Same-Board Connection
118
Table 35: Same-Board Connection
118
Power Considerations
119
Specific Signals
119
PCI Express (Pcie) Interface 2.0
121
Connectivity
121
Table 36: Signal Groups
121
Table 37: Specific Device
121
Figure 60: PCI Express Interface Connectivity
122
Interface Signals Layout Guidelines
123
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell ® Device
123
Figure 62: Topology with an Existing Connector And/Or an Add-In Card
124
Table 38: System Board with Existing Connector
124
Table 39: Add-In Card
126
Figure 63: Topology with a Same-Board Connection
127
Table 40: Same-Board Connection
127
Power Considerations
129
Reference Clock Considerations
129
Specific Signals
129
Universal Serial Bus (USB) 2.0 Interface
130
Interface Connectivity
130
Figure 64: USB 2.0 Interface Connectivity to a Connector-Including Optional Common Mode Choke and Protection Diodes Circuitry
130
Table 25: Signal Groups
130
Table 27: Signal Groups
130
Table 41: USB Interface Pin Connectivity Groups
130
Figure 65: Vbus Connectivity When Configured as a Host
131
Figure 66: Vbus Connectivity When Configured as a Device
131
Interface Signals Layout Guidelines
132
Figure 67: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device
132
Table 42: Routing Constraints When Configured as a Device
132
Figure 68: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host
134
Table 43: Routing Constraints When Configured as a Host
134
Power Considerations
135
Specific Signals
135
Universal Serial Bus (USB) 3.0 Interface
136
General Design Considerations
136
Interface Connectivity
136
Table 44: USB Interface Pin Connectivity Groups
136
Figure 69: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device
137
Table 45: Routing Constraints When Configured as a Device
137
Figure 70: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host
139
Table 46: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry- When Configured as a Host
139
Serial ATA (SATA) Interface 3.0
141
Connectivity
141
Interface Signals Layout Guidelines
141
Figure 71: SATA Interface Connectivity
141
Table 47: Signal Groups
141
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable
142
Table 48: Connection to a Standard SATA 3.0 1-Meter Cable
142
Clock Considerations
143
Power Considerations
143
Specific Signals
143
SDIO 3.0 and MMC 4.4
144
Interface Connectivity
144
Connectivity
144
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side
144
Table 49: Signal Groups
144
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology
145
Table 50: Routing Constraints for SDIO 3.0 and MMC 4.4 Interfaces
145
Serial Management Interface (SMI)
147
Interface Connectivity
147
Interface Signals Layout Guidelines
147
Figure 75: Clock Transition Examples
148
Figure 76: Master SMI Connectivity Example
148
Device Bus Interface
149
Device Bus Interface Connectivity
149
Figure 77: Using Two 8-Bit Flash Devices to Comprise a 16-Bit Bus
149
Figure 78: Example of a 16-Bit Wide Device Connection
150
Figure 79: Example of a 512 KB Flash Device with an 8-Bit Data Bus Connection
151
Dev_Readyn Support
152
Device Bus Interface Control Signals at Reset
152
Figure 80: Dev_Readyn Connection Example
152
NAND Flash Support
153
Figure 81: Connectivity for Chip Enable Don't Care NAND Flash
153
General Clock Guidelines
154
Core Clock
155
Figure 82: Core Clock Connectivity
155
Table 51: Core Clock Tx/Rx Path Constraints
155
Figure 83: Reference Clock Distribution
156
ARMADA ® 38X Family Clock Topology
157
Clock Topology
157
Figure 84: Clock Topology
157
PCI Express Clock Topology
158
Figure 85: Internal Reference Clock with up to 2 Pcie Root Complex Ports
158
Figure 86: External Reference Clock with 4 Pcie Root Complex Ports
159
Figure 87: External Reference Clock with 1 Pcie Endpoint and 3 Root Complex Ports
159
Figure 88: Internal Reference Clock Topology with 4 Pcie Root Complex Ports
160
Figure 89: Internal Reference Clock Topology with 1 Pcie Endpoint and 3 Root Complex Ports
160
Adaptive Voltage Scaling (AVS)
161
Connectivity
161
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection
162
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage
162

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Marvell ARMADA 88F6810 Hardware Design Manual (163 pages)

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