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A 10.4 inch color Liquid Crystal Display, along with
supporting components Display Interface Board and
Backlight Inverter Board are mounted on a plate that
is at tached to the OptiView Control Center door. A clear
plexiglass face plate prevents display surface damage.
System op er at ing parameters are displayed on various
color graph ic screens. The various display screens are
se lect ed for display using the Keypad keys.
The Display provided in the new chiller or from YORK
as a service replacement part, could be manufactured by
any of several approved manufacturers. Each Dis play
requires a specifi c Display Interface Board, Back light
Inverter Board, Inverter Board interface cable and Pro-
gram command set. There fore, Service re place ment
Displays or sup port ing com po nents cannot be ar-
bi trari ly selected!!! As explained below, re place ment
Displays are provided from YORK as kits to as sure
com pat i bil i ty of all com po nents. Non-com pat i bil i ty
of com po nents will result in incorrect op er a tion!!!
Refer to "Display In ter face Board" and "Back light In-
vert er Board" sections that follow this section. Dis plays
that could be provided from YORK in new chillers or
as re place ment parts are:
• SHARP LQ10D367
• SHARP LQ10D421
• NEC NL6448AC33-24
• LG SEMICON LP104V2-W
The YORK part numbers of the Display Interface
Board, Backlight Inverter Board and Inverter ribbon
cable pro vid ed, are listed on a label attached to the
Display mount ing plate. These are the part numbers of
the sup port ing components that are compatible with the
in stalled dis play. These supporting components can be
individually replaced. However, if the Liquid Crystal
Display fails, Display replacement kit 331-01771-000
must be or dered as detailed below. This kit contains
a replacement Dis play and all compatible supporting
com po nents.
The Display has 307,200 pixels arranged in a 640 col-
umns X 480 rows matrix confi guration. Each pixel con-
sists of 3 windows; red, green and blue, through which
a variable amount of light from the Display Backlight
is permitted to pass through the front of the display.
Im bed ded in each window of the pixel is a transistor,
YORK INTERNATIONAL
SECTION 5
LIQUID CRYSTAL DISPLAY
(REFER TO FIG. 18 - 27)
the conduction of which determines the amount of light
that will pass through the window. The conduction of
each transistor is controlled by a signal from the Dis play
Con trol ler on the Microboard. The overall pixel color
is a result of the gradient of red, green and blue light
al lowed to pass.
Under Program control, the Display Controller on the
Microboard sends a drive signal for each pixel to cre ate
the image on the display. Each pixel's drive signal is an
18 bit binary word; 6 bits for each of the 3 colors, red
green and blue. The greater the binary value, the great er
the amount of light permitted to pass. The col umns of
pixels are driven from left to right and the rows are
driven top to bottom. To coordinate the drive sig nals
and assure the columns are driven from left to right
and the rows are driven from top to bottom, each drive
sig nal contains a horizontal and vertical sync signal. The
Display Interface Board receives these dis play drive
sig nals from the Microboard J5 and applies them to the
Dis play at connector CN1. Refer to Fig. 28.
Although there are variations in control signal timing
between different display manufacturers, Fig. 23 de picts
typical control signals. Since these control sig nals occur
at rates greater than can be read with a Volt me ter, the
following description is for information only. There are
480 horizontal rows of pixels. Each row con tains 640
3-window pixels. Beginning with the top row, the drive
signals are applied within each row, se quen tial ly left
to right, beginning with the left most pixel and end ing
with the right most pixel. The rows are driv en from top
to bottom. The Vertical Sync (VSYNC) pulse starts the
scan in the upper left corner. The fi rst Horizontal Sync
(HSYNC) pulse initiates the se quen tial ap pli ca tion of
RGB drive signals to the 640 pixels in row 1. Upon
receipt of the ENABLE signal, an RGB drive signal
is applied to the fi rst pixel. As long as the EN ABLE
signal is present, RGB drive signals are then applied to
the remaining 639 pixels at the CLK rate of 25.18M Hz,
or one every 39.72 nanoseconds. Typically it takes 31
microseconds to address all 640 pixels. Sim i lar ly, the
next HSYNC pulse applies drive signals to row 2. This
continues until all 480 rows have been ad dressed. Total
elapsed time to address all 480 rows is ap prox i mate ly 16
milliseconds. The next VSYNC pulse causes the above
cycle to repeat. Displays can be op er at ed in FIXED
mode or DISPLAY ENABLE mode. In FIXED mode,
the fi rst pixel drive signal is applied a fi xed number
FORM 160.54-M1(503)
5
45
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