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Microboard
cro con fi g ures the FPGA to control the Digital Outputs.
Dur ing chiller operation, the Micro controls the Digital
Outputs by writ ing the de sired output state, logic low
(<+1VDC) or logic high (+VDC) to the FPGA. Writ-
ing a logic high ac tu al ly turns off the output, allowing
it to be pulled up by the source voltage applied to the
de vice connected to this out put. These voltages could
be +5VDC, +12VDC or +24VDC. There fore, when the
Micro turns off the out put, the ac tu al volt age measured at
the out put will vary ac cord ing to the volt age con nect ed
to this out put. The FPGA latches and holds this state until
changed by the Micro. The Mi cro controls the relays and
triacs on the I/O Board (via Microboard J19) by writing
the de sired state to the FPGA. To en er gize a relay or turn
on a triac, the FPGA output is a logic low voltage level
(<+1VDC). To de-en er gize a relay or turn off a triac,
the output is a logic high volt age level (+12VDC). The
out puts that con trol the com pres sor mo tor start relay
(K13 on I/O Board) and the chilled water pump start/
stop relay (K0 on I/O Board) have anti-recycle timers
as so ci at ed with them. The out put that con trols K13 will
not change at a rate greater than once every 20 sec onds.
The output that con trols K0 will not change at a rate
greater than once every 10 seconds. The FPGA is used
to read the keypad (via Microboard J5) to de ter mine if
any keys are being pressed. The keypad is a ma trix of
conductors ar ranged in rows and columns (ref. Fig. 32
& 33). There are 4 rows and 8 columns. When a key is
pressed, the con duc tors are pressed together at that point,
creating continuity be tween that row con duc tor and the
column con duc tor. The Key pad is read by applying a
log ic low to a row while leaving +5VDC pullup on all
the other rows. The Micro then reads the 8 columns. If
any col umn has a logic low on it, the key corresponding
to that co or di nate (row, column) is being pressed. The
Micro reads the en tire Keypad by re peat ing this routine
be gin ning with row 1 and ending with row 4. The entire
Keypad is read ev ery Program cycle. The Mi cro se lects
the MUX inputs (Microboard J7, J8, J9) for in put to the
A/D Converter by writing se quen tial ad dress es to the
FPGA. The FPGA holds each ad dress until a new one
is re ceived from the Mi cro. As each address is ap plied
to the MUX, the input cor re spond ing to that ad dress
is passed through the MUX to the A/D Con vert er. The
22
A/D Converter will con vert the an a log value to a digital
word when the Micro writes a "start con ver sion" pulse to
the FPGA. The FPGA pass es this to the A/D Con vert er.
The Micro retrieves cer tain op er at ing pa ram e ters (via
Microboard J10) from the com pres sor mo tor starter con-
trol board (CM-2 Current Mod ule or Mod "A" Solid
State Starter Logic Board) by writ ing ad dress es to it
via the FPGA. The ad dress es, 0 through 7 are writ ten
se quen tial ly. On the starter con trol board is an 8 chan nel
MUX. As each address is received by the start er control
board MUX, it causes the ap pro pri ate an a log value to
be passed to the Microboard as an analog input and
pro cessed as de scribed above. The Micro de ter mines
the type of start er ap plied by the volt age re ceived from
channel 0. A volt age of <0.4VDC in di cates the start er
is electro-me chan i cal type; > 0.4VDC in di cates starter
type is Mod "A" solid state. If it de ter mines there is an
electro-me chan i cal start er present, it reads chan nel 7 and
pro cess es the 0-4VDC output and dis plays it as %FLA.
If it de ter mines there is a Mod "A" solid state starter
present, the channel 0 volt age indicates the starter size
(model) and voltmeter range (300V or 600V). Channel 1
is a hardware gen er at ed current limit command that will
force current limit con trol at 100%FLA (prevent vanes
from opening) and 104%FLA (drive vanes closed until
current <102%), regardless of the software cur rent limit
operation. Chan nels 2 through 4 are analog voltages that
represent phase A, B and C motor cur rent. Channels 5
through 7 are an a log volt ag es that rep re sent Phase A,
B and C line voltage.
The addresses and associated data are shown below.
CM-2 Board
Solid State Starter Logic Board
Address
Data
Address
0 thru 6
Gnd
0
1
Peak
2 - 4
7
Motor
Current
5 - 7
FORM 160.54-M1(503)
Mod "A"
Data
starter model /
volt me ter range
cur rent limit command
phase C, B, A
motor current
phase A, B, C
line voltage
YORK INTERNATIONAL
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