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6-14
TECHNICAL DATA
Component-Level Description:
The differential digital input signal is received through a shielded 1:1 pulse trans-
former (T602). T602 has very low inter-winding capacitance, providing a high
level of isolation for high frequency common mode interference. IC610 is a dedi-
cated AES/EBU digital audio receiver integrated circuit. It contains a phase
locked loop that recovers the clock and the synchronization information present in
the AES/EBU signal. A Schmitt trigger at the input provides 50mV of hysteresis
for added noise immunity. R616 provides a 110Ω input impedance per the
AES/EBU specification.
AES receiver chip IC610 communicates with the Z-180 via control registers and
data memory accessed through the parallel port made up of the 4-bit address bus
(pins 15-18), the 8-bit data bus (pins 1-6, 27-28) and the
pins (pins 23 and 24).
The data consists of input sample rate and signal validity/error information from
the AES stream.
The AES receiver outputs the master clock on pin 19, the bit clock on pin 12, and
the frame clock on pin 11. The MCK clock output at pin 19 of the AES receiver
chip has a frequency 256 times the input sample rate of the received signal. These
clocks are used to drive the output AES/EBU transmitter when an output sample
rate that is synchronous to the sync input sample rate (external sync) is required.
Output Circuits
This circuitry interfaces the DSP to the analog and digital audio outputs. The digital au-
dio from the DSP is transmitted to the digital-to-analog converter (D/A) and output sam-
ple rate converter (SRC). The digital-to-analog (D/A) converter converts the digital au-
dio words generated by the DSP to analog output audio. The analog output stages scale
and buffer the D/A output signal to drive the analog output XLR connectors with a low
impedance balanced output. The digital output transmitter accepts the digital audio
words from the output sample rate converter (SRC) and transmits them in AES/EBU-
format digital audio signals on the digital output connector.
1. Stereo Digital-to-Analog (D/A) Converter
The D/A is a stereo, 20-bit delta-sigma converter. It receives the serial left and right au-
dio data samples from the DSP circuits.
For information on 6200 system clocking, please refer to "12.288MHz Oscillator and
System Clocking."
Component-Level Description:
IC400 is the digital-to-analog (D/A) converter for the left and right analog moni-
tor output signals. The synchronous serial input interface consists of the serial
data input (SDATA), serial data clock (SCLK), and the left/right clock (LRCK).
This interface is configured via DIF∅, DIF1, and DIF2 pins for 20-bit left justi-
Orban Model 6200
and
control
C
S
RD/
WR
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