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used to synthesize an 18.432MHz clock for operating the host microprocessor at an in-
ternal 9.216MHz rate, which the serial ports utilize to support RS-232 communications.
Component-Level Description:
The 12.288MHz digital output from crystal oscillator Y602 is buffered by IC606-
C, which feeds digital multiplexer chip IC609. This in turn routes the 12.288MHz
to AES/EBU digital audio transmitter chip IC603 when an internally generated
32kHz or 48kHz output sample rate is selected. The 12.288MHz clock is also sent
to an 8-bit synchronous counter implemented in programmable logic array (PLA)
IC613. This counter divides down to obtain the lower frequency system clocks.
All outputs of the PLA have their transitions coincident with the rising edge of the
12.288MHz clock. The 12.288MHz clock is inverted by buffers IC605-A, -B to
provide clocks
with the transitions of the lower frequency clocks.
of the inter-DSP communication links following buffers IC710-B, -D.
12.288MHZB
Y601 feeds the master clock (MCLK) inputs of both the input and output SRC
chips IC601 and IC603.
The 6.144MHz clock output from IC613 feeds the PLL circuit made up of PLA
IC618, 74HC4046 phase detector/VCO IC619 and associated components. The
PLA first buffers the 6.144MHz signal, providing a clean 6.144MHz output at pin
12 used as the reference input to the PLL phase detector (IC619 pin 14). Of the
three detectors included in the 74HC4046, the phase frequency detector (PFD) is
used by the 6200. The output of the phase detector (pin 13) feeds the loop filter
made up of resistors R607, R608 and capacitor C605 that provide a single pole
low-pass filter forming a second order loop. Pin 9 of IC619 is the input control
voltage to the VCO. Resistor R614 eliminates subharmonic frequency modulation
of the VCO caused by parasitic capacitance. Resistors R605 and R606 set the
PLL's lock-in frequency range. A divide-by-three counter is placed between the
VCO output and the phase detector comparator input. This places the VCO output
at 18.432MHz. The divide-by-three is implemented by the PLA IC618 between
pins 2 and 16. A 4.096MHz clock is provided at pin 17 of the PLA. The PLA pro-
vides an 18.432MHz output at pin 14 which feeds Z-180 microprocessor IC100
via buffer IC201-A.
Inverter IC605-C provides the
buffer IC606-B, the bit clock for the input SRC, IC615.
IC614-A, -D provide buffered clocks 6.144MHZA and 6.144MHZB for driving
the EXTAL inputs (pin 27) of the DSP chips. Each buffer drives four DSP chips.
The 192kHz clock output of IC613 (pin 14) is used for the inter-DSP word clock.
The 192kHz, 96kHz and 48kHz clocks are all used in the LCD backlight drive
circuit. The 48kHz clock also provides, via buffers IC606-A and IC607-C, the
word clock interfacing the DSP to the input and output SRC chips and the A/D
and D/A converters. The 48kHz clock is used to generate DSP interrupt request
signals (IRQBA, IRQBB) required for process timing and interchip synchroniza-
tion. The circuit consisting of flip-flop IC612 and IC614-B, -C is required to en-
sure that the first falling edges of all IRQB signals are coincident. This synchroni-
and
12.288MHZA
12.288MHZB
feeds the A/D and D/A master clocks. 17.000MHz crystal oscillator
. 6
144
MHZ
that have falling edges coincident
feeds the bit clock
12.288MHZA
bit clock for the output D/A and, via
6-7
TECHNICAL DATA
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