Table Of Contents - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 7
AC Specifications .......................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Differences Between AD9776/AD9778/ AD9779 and
AD9776A/AD9778A/AD9779A............................................... 25
3-Wire Interface .............................................................................. 26
General Operation of the Serial Interface ............................... 26
Instruction Byte .......................................................................... 26
Serial Interface Port Pin Descriptions ..................................... 27
MSB/LSB Transfers..................................................................... 27
3-Wire Interface Register Map ...................................................... 28
Interpolation Filter Architecture .................................................. 33
Interpolation Filter Bandwidth Limits .................................... 37
Inverse Sinc Filter ....................................................................... 38
Sourcing the DAC Sample Clock ................................................. 39
Direct Clocking .......................................................................... 39
Clock Multiplication .................................................................. 39
Driving the REFCLK Input ....................................................... 42
Full-Scale Current Generation ..................................................... 43
Internal Reference ...................................................................... 43
Gain and Offset Correction .......................................................... 44
I/Q Channel Gain Matching ..................................................... 44
Auxiliary DAC Operation ......................................................... 44
LO Feedthrough Compensation .............................................. 45
Results of Gain and Offset Correction .................................... 45
Input Data Ports ............................................................................. 46
Single Port Mode ........................................................................ 46
Dual Port Mode .......................................................................... 46
Input Data Referenced to DATACLK ...................................... 46
Input Data Referenced to REFCLK ......................................... 47
Optimizing the Data Input Timing .......................................... 48
Device Synchronization ................................................................. 49
Synchronization Logic Overview ............................................. 49
Synchronizing Devices to a System Clock .............................. 50
Interrupt Request Operation .................................................... 50
Power Dissipation ........................................................................... 51
Power-Down and Sleep Modes................................................. 52
Evaluation Board Overview .......................................................... 53
Evaluation Board Operation ..................................................... 53
Outline Dimensions ....................................................................... 55
Ordering Guide .......................................................................... 55
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