3-Wire Interface Register Map - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A

3-WIRE INTERFACE REGISTER MAP

Note that all unused register bits should be kept at the device default values.
Table 13.
Address
Register
Name Hex Decimal
Comm 0x00 00
Digital 0x01 01
Control
0x02 02
Sync 0x03 03
Control
0x04 04
0x05 05
0x06 06
0x07 07
PLL 0x08 08
Control
0x09 09
Misc. 0x0A 10
Control
I DAC 0x0B 11
Control
0x0C 12
Aux 0x0D 13
DAC1
0x0E 14
Control
Q DAC 0x0F 15
Control
0x10 16
Aux 0x11 17
DAC2
0x12 18
Control
0x13 19 to 24
to
0x18
Interrupt 0x19 25
Version 0x1F 31
Bit 7 Bit 6
SDIO LSB/MSB
bidirectional first
Interpolation Factor[1:0]
Data format Single port
DATACLK Reserved
delay mode (set to 1)
DATACLK Delay[3:0]
SYNC_O Delay[3:0]
SYNC_I Delay[3:0]
SYNC_I SYNC_O
enable enable
PLL Band Select[5:0]
PLL enable PLL VCO Divide Ratio[1:0]
VCO Control Voltage[2:0] (read only)
I DAC sleep I DAC
power-
down
Auxiliary Auxiliary
DAC1 sign DAC1
current
direction
Q DAC sleep Q DAC
power-
down
Auxiliary Auxiliary
DAC2 sign
DAC2
current
direction
Data timing Sync timing
error IRQ error IRQ
Bit 5 Bit 4 Bit 3
Software Power- Auto
reset down power-
mode down
enable
Filter Modulation Mode[3:0]
Real mode DATACLK Inverse
delay sinc
enable enable
DATACLK Divide[1:0]
SYNC_O
triggering
edge
PLL Loop Divide
Ratio[1:0]
I DAC Gain Adjustment[7:0]
Auxiliary DAC1 Data[7:0]
Auxiliary
DAC1
power-
down
Q DAC Gain Adjustment[7:0]
Auxiliary DAC2 Data[7:0]
Auxiliary
DAC2
power-
down
Reserved
Data Data
timing timing
error type error
IRQ
enable
Version[7:0]
Rev. B | Page 28 of 56
Bit 2 Bit 1
PLL lock
indicator
(read
only)
DATACLK
Delay[4]
DATACLK TxEnable
invert invert
Data Timing Margin[3:0]
SYNC_O Divide[2:0]
SYNC_I Ratio[2:0]
SYNC_I Timing Margin[3:0]
Clock State[4:0]
PLL VCO Drive[1:0]
PLL Bias[2:0]
PLL Loop Bandwidth[4:0]
I DAC Gain
Adjustment[9:8]
Auxiliary DAC1
Data[9:8]
Q DAC Gain
Adjustment[9:8]
Auxiliary DAC2
Data[9:8]
Sync
timing
error IRQ
enable
Bit 0 Def.
0x00
Zero 0x00
stuffing
enable
Q first 0x00
0x00
SYNC_O 0x00
Delay[4]
SYNC_I 0x00
Delay[4]
0x00
0x00
0xE7
0x52
0x1F
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
Internal 0x00
sync
loopback
0x07