Input Data Referenced To Refclk - Analog Devices AD9776A Manual

The DATACLKDIV only affects the DATACLK output frequency,
not the frequency of the data sampling clock. To maintain an
f frequency that samples the input data that remains
DATACLK
consistent with the expected data rate, DATACLKDIV should
be set to 00.
Table 27. DACCLK to DATACLK Divisor Values
Variable Value
IF Interpolation factor (1, 2, 4,
or 8)
ZS 1, if zero stuffing is disabled
2, if zero stuffing is enabled
SP 0.5, if single port is enabled
1, if dual port is selected
DATACLKDIV 1, 2, or 4

INPUT DATA REFERENCED TO REFCLK

In some systems, it may be more convenient to use the REFCLK
input than the DATACLK output as the input data timing
reference. If the frequency of DACCLK is equal to the frequency
of the data input (without interpolation), then the data with
respect to REFCLK± timing specifications in Table 28 apply
directly without further considerations. If the frequency of
DACCLK is greater than the frequency of the input data, a
divider is used to generate the DATACLK output (and the
internal data sampling clock). This divider creates a phase
ambiguity between REFCLK and DATACLK, which results in
uncertainty in the sampling time. To establish fixed setup and
hold times of the data interface, this phase ambiguity must be
eliminated.
To eliminate the phase ambiguity, the SYNC_I input pins (Pin 13
and Pin 14) must be used to force the data to be sampled on a
specific REFCLK edge. The relationship among REFCLK,
SYNC_I, and input data is shown in Figure 84 and Figure 85.
Therefore, both SYNC_I and data must meet the timing in
Table 28 for reliable data transfer into the device.
Table 28. Data Timing Specifications vs. Temperature
Timing Parameter
Data with Respect to REFCLK±
Data with Respect to DATACLK
SYNC_I± to REFCLK±
Address
Register Bit
0x01 [7:6]
0x01 [0]
0x02 [6]
0x03 [5:4]
Temperature Min t (ns)
S
−40°C −0.80
+25°C −1.00
+85°C −1.10
−40°C to +85°C −0.80
−40°C 2.50
+25°C 2.70
+85°C 3.00
−40°C to +85°C 3.00
−40°C 0.30
+25°C 0.25
+85°C 0.15
−40°C to +85°C 0.30
Rev. B | Page 47 of 56
AD9776A/AD9778A/AD9779A
SYNC_I
REFCLK
DATA
Figure 84. Input Data Port Timing, Data Referenced to REFCLK, f
Note that even though the setup and hold times of SYNC_I
are relative to REFCLK, the SYNC_I input is sampled at the
internal DACCLK rate. In the case where the PLL is employed,
SYNC_I must be asserted to meet the setup time with respect to
REFCLK (t ), but cannot be asserted prior to the previous
S_SYNC
rising edge of the internal SYNC_I sample clock. In other words,
the SYNC_I assert edge has to be placed between its successive
keep out windows that replicate at the DACCLK rate, not the
REFCLK rate. The valid window for asserting SYNC_I is
shaded gray in Figure 85 for the case where the PLL provides a
DACCLK frequency of four times the REFCLK frequency.
Thus, the minimum setup time is t
setup time is t
DACCLK
SYNC_I
REFCLK
DACCLK
t
SREFCLK
DATA
Figure 85. Input Data Port Timing, Data Referenced to REFCLK,
More details of the synchronization circuitry are found in the
Device Synchronization section of this data sheet.
PLL Disabled
Min t (ns) Min KOW (ns)
H
3.35 2.55
3.50 2.50
3.80 2.70
3.80 3.00
−0.05 2.45
−0.20 2.50
−0.40 2.60
−0.05 2.95
0.65 0.95
0.75 1.00
0.90 1.05
0.90 1.20
t
H_SYNC
t
S_SYNC
t
SREFCLK
t
HREFCLK
, and the maximum
S_SYNC
− t .
H_SYNC
t
DACCLK
t
H_SYNC
t
S_SYNC
t
HREFCLK
f = f × 4
DACCLK REFCLK
PLL Enabled
Min t (ns) Min t (ns)
S H
−0.83 3.87
−1.06 4.04
−1.19 4.37
−0.83 4.37
2.50 −0.05
2.70 −0.20
3.00 −0.40
3.00 −0.05
0.27 1.17
0.19 1.29
0.06 1.47
0.27 1.47
= f
DACCLK REFCLK
Min KOW (ns)
2.99
2.98
3.16
3.54
2.45
2.50
2.60
2.95
1.39
1.48
1.51
1.74