Xilinx KC705 User Manual page 90

Appendix C: Master Board Constraints
set_property PACKAGE_PIN U8 [get_ports PCIE_CLK_QO_P]
set_property PACKAGE_PIN V2 [get_ports PCIE_TX6_P]
set_property PACKAGE_PIN Y6 [get_ports PCIE_RX6_P]
set_property PACKAGE_PIN V1 [get_ports PCIE_TX6_N]
set_property PACKAGE_PIN Y5 [get_ports PCIE_RX6_N]
set_property PACKAGE_PIN Y2 [get_ports PCIE_TX7_P]
set_property PACKAGE_PIN AA4 [get_ports PCIE_RX7_P]
set_property PACKAGE_PIN Y1 [get_ports PCIE_TX7_N]
set_property PACKAGE_PIN AA3 [get_ports PCIE_RX7_N]
set_property PACKAGE_PIN L4 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN M6 [get_ports PCIE_RX0_P]
set_property PACKAGE_PIN L3 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN M5 [get_ports PCIE_RX0_N]
set_property PACKAGE_PIN M2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN P6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN M1 [get_ports PCIE_TX1_N]
set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]
set_property PACKAGE_PIN P5 [get_ports PCIE_RX1_N]
set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N]
set_property PACKAGE_PIN N7 [get_ports FMC_LPC_GBTCLK0_M2C_C_N]
set_property PACKAGE_PIN N8 [get_ports FMC_LPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN N4 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN R4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN N3 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN R3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN P2 [get_ports PCIE_TX3_P]
set_property PACKAGE_PIN T6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN P1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN T5 [get_ports PCIE_RX3_N]
set_property PACKAGE_PIN F2 [get_ports FMC_LPC_DP0_C2M_P]
set_property PACKAGE_PIN F6 [get_ports FMC_LPC_DP0_M2C_P]
set_property PACKAGE_PIN F1 [get_ports FMC_LPC_DP0_C2M_N]
set_property PACKAGE_PIN F5 [get_ports FMC_LPC_DP0_M2C_N]
set_property PACKAGE_PIN H2 [get_ports SFP_TX_P]
set_property PACKAGE_PIN G4 [get_ports SFP_RX_N]
set_property PACKAGE_PIN H1 [get_ports SFP_TX_N]
set_property PACKAGE_PIN G8 [get_ports SGMIICLK_Q0_P]
set_property PACKAGE_PIN G3 [get_ports SFP_RX_P]
set_property PACKAGE_PIN G7 [get_ports SGMIICLK_Q0_N]
set_property PACKAGE_PIN J7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN J8 [get_ports SMA_MGT_REFCLK_P]
set_property PACKAGE_PIN J4 [get_ports SGMII_TX_P]
set_property PACKAGE_PIN H6 [get_ports SGMII_RX_P]
set_property PACKAGE_PIN J3 [get_ports SGMII_TX_N]
set_property PACKAGE_PIN H5 [get_ports SGMII_RX_N]
set_property PACKAGE_PIN K2 [get_ports SMA_MGT_TX_P]
set_property PACKAGE_PIN K6 [get_ports SMA_MGT_RX_P]
set_property PACKAGE_PIN K1 [get_ports SMA_MGT_TX_N]
set_property PACKAGE_PIN K5 [get_ports SMA_MGT_RX_N]
set_property PACKAGE_PIN A4 [get_ports FMC_HPC_DP3_C2M_P]
set_property PACKAGE_PIN A8 [get_ports FMC_HPC_DP3_M2C_P]
set_property PACKAGE_PIN A3 [get_ports FMC_HPC_DP3_C2M_N]
set_property PACKAGE_PIN A7 [get_ports FMC_HPC_DP3_M2C_N]
set_property PACKAGE_PIN B2 [get_ports FMC_HPC_DP2_C2M_P]
set_property PACKAGE_PIN B6 [get_ports FMC_HPC_DP2_M2C_P]
set_property PACKAGE_PIN B1 [get_ports FMC_HPC_DP2_C2M_N]
set_property PACKAGE_PIN C8 [get_ports FMC_HPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN B5 [get_ports FMC_HPC_DP2_M2C_N]
set_property PACKAGE_PIN C7 [get_ports FMC_HPC_GBTCLK0_M2C_C_N]
set_property PACKAGE_PIN E7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N]
set_property PACKAGE_PIN E8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]
set_property PACKAGE_PIN C4 [get_ports FMC_HPC_DP1_C2M_P]
set_property PACKAGE_PIN D6 [get_ports FMC_HPC_DP1_M2C_P]
set_property PACKAGE_PIN C3 [get_ports FMC_HPC_DP1_C2M_N]
set_property PACKAGE_PIN D5 [get_ports FMC_HPC_DP1_M2C_N]
set_property PACKAGE_PIN D2 [get_ports FMC_HPC_DP0_C2M_P]
set_property PACKAGE_PIN E4 [get_ports FMC_HPC_DP0_M2C_P]
set_property PACKAGE_PIN D1 [get_ports FMC_HPC_DP0_C2M_N]
set_property PACKAGE_PIN E3 [get_ports FMC_HPC_DP0_M2C_N]
90 www.xilinx.com KC705 Evaluation Board
UG810 (v1.4) July 18, 2013