Xilinx KC705 User Manual page 88

Appendix C: Master Board Constraints
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN AD11 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
set_property PACKAGE_PIN AG10 [get_ports DDR3_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
set_property PACKAGE_PIN AH10 [get_ports DDR3_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
set_property PACKAGE_PIN AE10 [get_ports DDR3_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
set_property PACKAGE_PIN AF10 [get_ports DDR3_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
set_property PACKAGE_PIN AJ9 [get_ports DDR3_TEMP_EVENT]
set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT]
set_property PACKAGE_PIN AK9 [get_ports DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
set_property PACKAGE_PIN AG9 [get_ports DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
set_property PACKAGE_PIN AH9 [get_ports DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
set_property PACKAGE_PIN AK11 [get_ports DDR3_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
set_property PACKAGE_PIN AK10 [get_ports DDR3_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
set_property PACKAGE_PIN AH11 [get_ports DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
set_property PACKAGE_PIN AJ11 [get_ports DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
set_property PACKAGE_PIN AE13 [get_ports DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN AF13 [get_ports DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN AK14 [get_ports DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
set_property PACKAGE_PIN AK13 [get_ports DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
set_property PACKAGE_PIN AH14 [get_ports DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
set_property PACKAGE_PIN AJ14 [get_ports DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
set_property PACKAGE_PIN AJ13 [get_ports DDR3_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
set_property PACKAGE_PIN AJ12 [get_ports DDR3_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
set_property PACKAGE_PIN AF12 [get_ports DDR3_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
set_property PACKAGE_PIN AG12 [get_ports DDR3_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
set_property PACKAGE_PIN AG13 [get_ports DDR3_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
set_property PACKAGE_PIN AH12 [get_ports DDR3_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
set_property PACKAGE_PIN AD13 [get_ports VRP_33]
set_property PACKAGE_PIN AC6 [get_ports GPIO_SW_W]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_W]
set_property PACKAGE_PIN AD4 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
set_property PACKAGE_PIN AD3 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN AC2 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN AC1 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
set_property PACKAGE_PIN AD2 [get_ports DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
set_property PACKAGE_PIN AC5 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN AC4 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN AD6 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN AE6 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN AC7 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
set_property PACKAGE_PIN AD7 [get_ports VTTVREF]
set_property PACKAGE_PIN AF3 [get_ports DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
set_property PACKAGE_PIN AF2 [get_ports DDR3_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
88 www.xilinx.com KC705 Evaluation Board
UG810 (v1.4) July 18, 2013