Xilinx KC705 User Manual page 33

X-Ref Target - Figure 1-15
PCIe lane width/size is selected via jumper J32
selection is 8-lane (J32 pins 5 and 6 jumpered).
X-Ref Target - Figure 1-16
Table 1-11
Table 1-11: PCIe Edge Connector Connections
Schematic FPGA Pin
Net Name (U1)
PCIE_RX0_P M6
PCIE_RX0_N M5
PCIE_RX1_P P6
PCIE_RX1_N P5
PCIE_RX2_P R4
PCIE_RX2_N R3
PCIE_RX3_P T6
PCIE_RX3_N T5
PCIE_RX4_P V6
PCIE_RX4_N V5
PCIE_RX5_P W4
PCIE_RX5_N W3
PCIE_RX6_P Y6
PCIE_RX6_N Y5
PCIE_RX7_P AA4
PCIE_RX7_N AA3
PCIE_TX0_P L4
PCIE_TX0_N L3
KC705 Evaluation Board
UG810 (v1.4) July 18, 2013
P1
PCI Express
Eight-Lane
Edge connector
OE
GND
REFCLK+
REFCLK-
GND
Figure 1-15: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
Figure 1-16: PCI Express Lane Size Select Jumper J32
lists the PCIe edge connector connections.
PCIe Edge PCIe Edge Pin
Connector Pin Name
B14 PETp0
B15 PETn0
B19 PETp1
B20 PETn1
B23 PETp2
B24 PETn2
B27 PETp3
B28 PETn3
B33 PETp4
B34 PETn4
B37 PETp5
B38 PETn5
B41 PETp6
B42 PETn6
B45 PETp7
B46 PETn7
A16 PERp0
A17 PERn0
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C544
0.01μF 25V
A12
X7R
A13
PCIE_CLK_Q0_C_P
A14 PCIE_CLK_Q0_C_N
A15
C545
0.01μF 25V
X7R
GND
(Figure
J32
PCIE_PRSNT_B
1 2
3 4
5 6
UG810_c1_15_072511
Function
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block receive pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Feature Descriptions
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
UG810_c1_14_072511
1-16). The default lane size
FFG900
Placement
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y7
GTXE2_CHANNEL_X0Y7
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