Xilinx KC705 User Manual page 3

Date Version
05/10/2013 1.3
07/18/2013 1.4
UG810 (v1.4) July 18, 2013
Updated Figure 1-1 to show v 1.1 board. Updated
Fansink, callouts 25 and 26
FPGA Connections. Updated
address. Updated Table 1-17, page 37
Table 1-14, page 37. Updated
Semiconductor, deleted; updated
Figure 1-29, page 52 GPIO SMAs J13 and J14. Added Note to
Constraints. Updated Appendix D, Board
Updated Appendix G, Regulatory and Compliance Information
reference.
Revised the format of Table 1-20
U1 pin for FMC_HPC_CLK0_M2C_N
descriptions of the functions for SW13 position
Appendix C, Master Board
Listing to Master Board Constraints, replaced references to the term UCF with the term
XDC and replaced the KC705 Board UCF Listing with the
www.xilinx.com
Revision
Table 1-1, page
pointing to User I/O. Added
Programmable User Clock Source, page 27
for naming pins 18 and 19. Added Note to
I2C Bus Switch, page 47
[Ref 9]. Added Figure 1-28, page 52
Setup, step 1 of installation procedure.
and added the IO standard column. Revised the FPGA
in Table 1-28 to
3 and position
Constraints, changed appendix title from Master UCF
10: callout 1 to identify
Table 1-9, page 26 Source to
to include I
to show TI device instead of NXP
Rotary Switch, and
Appendix C, Master Board
to include CE PC Test
C27 on page 60. Revised the
5 in Table A-2. In
KC705 Board XDC Listing.
KC705 Evaluation Board
2
C